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[SPARC64]: Proper multi-core scheduling support.
The scheduling domain hierarchy is: all cpus --> cpus that share an instruction cache --> cpus that share an integer execution unit Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller
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David S. Miller
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Jun 5, 2007
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#ifndef _ASM_SPARC64_TOPOLOGY_H | ||
#define _ASM_SPARC64_TOPOLOGY_H | ||
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#ifdef CONFIG_SMP | ||
#include <asm/spitfire.h> | ||
#define smt_capable() (tlb_type == hypervisor) | ||
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#include <asm-generic/topology.h> | ||
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#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id) | ||
#define topology_core_id(cpu) (cpu_data(cpu).core_id) | ||
#define topology_core_siblings(cpu) (cpu_core_map[cpu]) | ||
#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu]) | ||
#define mc_capable() (tlb_type == hypervisor) | ||
#define smt_capable() (tlb_type == hypervisor) | ||
#endif /* CONFIG_SMP */ | ||
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#include <asm-generic/topology.h> | ||
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#define cpu_coregroup_map(cpu) (cpu_core_map[cpu]) | ||
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#endif /* _ASM_SPARC64_TOPOLOGY_H */ |