---

yaml
---
r: 235951
b: refs/heads/master
c: 6c66e94
h: refs/heads/master
i:
  235949: 24bb89e
  235947: 6da98d2
  235943: fe07f73
  235935: 1d36293
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: dab7f7fee09b28034af3cac527b16927e4e2a193
+refs/heads/master: 6c66e948d2c8254c8435f27eacb7f8657ce62dec

trunk/drivers/staging/tidspbridge/core/io_sm.c

@@ -118,9 +118,9 @@ struct io_mgr {
 	u32 ul_trace_buffer_begin;	/* Trace message start address */
 	u32 ul_trace_buffer_end;	/* Trace message end address */
 	u32 ul_trace_buffer_current;	/* Trace message current address */
-	u32 ul_gpp_read_pointer;	/* GPP Read pointer to Trace buffer */
+	u32 gpp_read_pointer;		/* GPP Read pointer to Trace buffer */
 	u8 *pmsg;
-	u32 ul_gpp_va;
+	u32 gpp_va;
 	u32 dsp_va;
 #endif
 	/* IO Dpc */
@@ -532,7 +532,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 				 * This is the virtual uncached ioremapped
 				 * address!!!
 				 */
-				ae_proc[ndx].ul_gpp_va = gpp_va_curr;
+				ae_proc[ndx].gpp_va = gpp_va_curr;
 				ae_proc[ndx].dsp_va =
 				    va_curr / hio_mgr->word_size;
 				ae_proc[ndx].ul_size = page_size[i];
@@ -542,7 +542,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 				dev_dbg(bridge, "shm MMU TLB entry PA %x"
 					" VA %x DSP_VA %x Size %x\n",
 					ae_proc[ndx].gpp_pa,
-					ae_proc[ndx].ul_gpp_va,
+					ae_proc[ndx].gpp_va,
 					ae_proc[ndx].dsp_va *
 					hio_mgr->word_size, page_size[i]);
 				ndx++;
@@ -557,7 +557,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 					"shm MMU PTE entry PA %x"
 					" VA %x DSP_VA %x Size %x\n",
 					ae_proc[ndx].gpp_pa,
-					ae_proc[ndx].ul_gpp_va,
+					ae_proc[ndx].gpp_va,
 					ae_proc[ndx].dsp_va *
 					hio_mgr->word_size, page_size[i]);
 				if (status)
@@ -580,12 +580,12 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 	 * should not conflict with shm entries on MPU or DSP side.
 	 */
 	for (i = 3; i < 7 && ndx < BRDIOCTL_NUMOFMMUTLB; i++) {
-		if (hio_mgr->ext_proc_info.ty_tlb[i].ul_gpp_phys == 0)
+		if (hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys == 0)
 			continue;
 
-		if ((hio_mgr->ext_proc_info.ty_tlb[i].ul_gpp_phys >
+		if ((hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys >
 		     ul_gpp_pa - 0x100000
-		     && hio_mgr->ext_proc_info.ty_tlb[i].ul_gpp_phys <=
+		     && hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys <=
 		     ul_gpp_pa + ul_seg_size)
 		    || (hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt >
 			ul_dsp_va - 0x100000 / hio_mgr->word_size
@@ -595,7 +595,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 				"CDB MMU entry %d conflicts with "
 				"shm.\n\tCDB: GppPa %x, DspVa %x.\n\tSHM: "
 				"GppPa %x, DspVa %x, Bytes %x.\n", i,
-				hio_mgr->ext_proc_info.ty_tlb[i].ul_gpp_phys,
+				hio_mgr->ext_proc_info.ty_tlb[i].gpp_phys,
 				hio_mgr->ext_proc_info.ty_tlb[i].dsp_virt,
 				ul_gpp_pa, ul_dsp_va, ul_seg_size);
 			status = -EPERM;
@@ -606,8 +606,8 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 				    dsp_virt;
 				ae_proc[ndx].gpp_pa =
 				    hio_mgr->ext_proc_info.ty_tlb[i].
-				    ul_gpp_phys;
-				ae_proc[ndx].ul_gpp_va = 0;
+				    gpp_phys;
+				ae_proc[ndx].gpp_va = 0;
 				/* 1 MB */
 				ae_proc[ndx].ul_size = 0x100000;
 				dev_dbg(bridge, "shm MMU entry PA %x "
@@ -618,7 +618,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 				status = hio_mgr->intf_fxns->brd_mem_map
 				    (hio_mgr->hbridge_context,
 				     hio_mgr->ext_proc_info.ty_tlb[i].
-				     ul_gpp_phys,
+				     gpp_phys,
 				     hio_mgr->ext_proc_info.ty_tlb[i].
 				     dsp_virt, 0x100000, map_attrs,
 				     NULL);
@@ -649,22 +649,22 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 	for (i = ndx; i < BRDIOCTL_NUMOFMMUTLB; i++) {
 		ae_proc[i].dsp_va = 0;
 		ae_proc[i].gpp_pa = 0;
-		ae_proc[i].ul_gpp_va = 0;
+		ae_proc[i].gpp_va = 0;
 		ae_proc[i].ul_size = 0;
 	}
 	/*
 	 * Set the shm physical address entry (grayed out in CDB file)
 	 * to the virtual uncached ioremapped address of shm reserved
 	 * on MPU.
 	 */
-	hio_mgr->ext_proc_info.ty_tlb[0].ul_gpp_phys =
+	hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys =
 	    (ul_gpp_va + ul_seg1_size + ul_pad_size);
 
 	/*
 	 * Need shm Phys addr. IO supports only one DSP for now:
 	 * num_procs = 1.
 	 */
-	if (!hio_mgr->ext_proc_info.ty_tlb[0].ul_gpp_phys || num_procs != 1) {
+	if (!hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys || num_procs != 1) {
 		status = -EFAULT;
 		goto func_end;
 	} else {
@@ -688,7 +688,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 						      ae_proc);
 		if (status)
 			goto func_end;
-		ul_shm_base = hio_mgr->ext_proc_info.ty_tlb[0].ul_gpp_phys;
+		ul_shm_base = hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys;
 		ul_shm_base += ul_shm_base_offset;
 		ul_shm_base = (u32) MEM_LINEAR_ADDRESS((void *)ul_shm_base,
 						       ul_mem_length);
@@ -740,7 +740,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 		goto func_end;
 	}
 
-	hio_mgr->ul_gpp_read_pointer = hio_mgr->ul_trace_buffer_begin =
+	hio_mgr->gpp_read_pointer = hio_mgr->ul_trace_buffer_begin =
 	    (ul_gpp_va + ul_seg1_size + ul_pad_size) +
 	    (hio_mgr->ul_trace_buffer_begin - ul_dsp_va);
 	/* Get the end address of trace buffer */
@@ -772,7 +772,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
 		status = -ENOMEM;
 
 	hio_mgr->dsp_va = ul_dsp_va;
-	hio_mgr->ul_gpp_va = (ul_gpp_va + ul_seg1_size + ul_pad_size);
+	hio_mgr->gpp_va = (ul_gpp_va + ul_seg1_size + ul_pad_size);
 
 #endif
 func_end:
@@ -1541,7 +1541,7 @@ static int register_shm_segs(struct io_mgr *hio_mgr,
 			goto func_end;
 		}
 		/* First TLB entry reserved for Bridge SM use. */
-		ul_gpp_phys = hio_mgr->ext_proc_info.ty_tlb[0].ul_gpp_phys;
+		ul_gpp_phys = hio_mgr->ext_proc_info.ty_tlb[0].gpp_phys;
 		/* Get size in bytes */
 		ul_dsp_virt =
 		    hio_mgr->ext_proc_info.ty_tlb[0].dsp_virt *
@@ -1693,48 +1693,48 @@ void print_dsp_debug_trace(struct io_mgr *hio_mgr)
 		ul_gpp_cur_pointer =
 		    *(u32 *) (hio_mgr->ul_trace_buffer_current);
 		ul_gpp_cur_pointer =
-		    hio_mgr->ul_gpp_va + (ul_gpp_cur_pointer -
+		    hio_mgr->gpp_va + (ul_gpp_cur_pointer -
 					  hio_mgr->dsp_va);
 
 		/* No new debug messages available yet */
-		if (ul_gpp_cur_pointer == hio_mgr->ul_gpp_read_pointer) {
+		if (ul_gpp_cur_pointer == hio_mgr->gpp_read_pointer) {
 			break;
-		} else if (ul_gpp_cur_pointer > hio_mgr->ul_gpp_read_pointer) {
+		} else if (ul_gpp_cur_pointer > hio_mgr->gpp_read_pointer) {
 			/* Continuous data */
 			ul_new_message_length =
-			    ul_gpp_cur_pointer - hio_mgr->ul_gpp_read_pointer;
+			    ul_gpp_cur_pointer - hio_mgr->gpp_read_pointer;
 
 			memcpy(hio_mgr->pmsg,
-			       (char *)hio_mgr->ul_gpp_read_pointer,
+			       (char *)hio_mgr->gpp_read_pointer,
 			       ul_new_message_length);
 			hio_mgr->pmsg[ul_new_message_length] = '\0';
 			/*
 			 * Advance the GPP trace pointer to DSP current
 			 * pointer.
 			 */
-			hio_mgr->ul_gpp_read_pointer += ul_new_message_length;
+			hio_mgr->gpp_read_pointer += ul_new_message_length;
 			/* Print the trace messages */
 			pr_info("DSPTrace: %s\n", hio_mgr->pmsg);
-		} else if (ul_gpp_cur_pointer < hio_mgr->ul_gpp_read_pointer) {
+		} else if (ul_gpp_cur_pointer < hio_mgr->gpp_read_pointer) {
 			/* Handle trace buffer wraparound */
 			memcpy(hio_mgr->pmsg,
-			       (char *)hio_mgr->ul_gpp_read_pointer,
+			       (char *)hio_mgr->gpp_read_pointer,
 			       hio_mgr->ul_trace_buffer_end -
-			       hio_mgr->ul_gpp_read_pointer);
+			       hio_mgr->gpp_read_pointer);
 			ul_new_message_length =
 			    ul_gpp_cur_pointer - hio_mgr->ul_trace_buffer_begin;
 			memcpy(&hio_mgr->pmsg[hio_mgr->ul_trace_buffer_end -
-					      hio_mgr->ul_gpp_read_pointer],
+					      hio_mgr->gpp_read_pointer],
 			       (char *)hio_mgr->ul_trace_buffer_begin,
 			       ul_new_message_length);
 			hio_mgr->pmsg[hio_mgr->ul_trace_buffer_end -
-				      hio_mgr->ul_gpp_read_pointer +
+				      hio_mgr->gpp_read_pointer +
 				      ul_new_message_length] = '\0';
 			/*
 			 * Advance the GPP trace pointer to DSP current
 			 * pointer.
 			 */
-			hio_mgr->ul_gpp_read_pointer =
+			hio_mgr->gpp_read_pointer =
 			    hio_mgr->ul_trace_buffer_begin +
 			    ul_new_message_length;
 			/* Print the trace messages */

trunk/drivers/staging/tidspbridge/core/tiomap3430.c

@@ -406,7 +406,7 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
 	ul_shm_offset_virt =
 	    ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
 	/* Kernel logical address */
-	ul_shm_base = dev_context->atlb_entry[0].ul_gpp_va + ul_shm_offset_virt;
+	ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
 
 	DBC_ASSERT(ul_shm_base != 0);
 	/* 2nd wd is used as sync field */

trunk/drivers/staging/tidspbridge/core/tiomap_io.c

@@ -137,7 +137,7 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
 			    dev_context->atlb_entry[0].dsp_va * DSPWORDSIZE;
 			DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
 			dw_ext_prog_virt_mem =
-			    dev_context->atlb_entry[0].ul_gpp_va;
+			    dev_context->atlb_entry[0].gpp_va;
 
 			if (!trace_read) {
 				ul_shm_offset_virt =
@@ -337,7 +337,7 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
 			    ul_shm_base_virt - ul_tlb_base_virt;
 			if (trace_load) {
 				dw_ext_prog_virt_mem =
-				    dev_context->atlb_entry[0].ul_gpp_va;
+				    dev_context->atlb_entry[0].gpp_va;
 			} else {
 				dw_ext_prog_virt_mem = host_res->mem_base[1];
 				dw_ext_prog_virt_mem +=

trunk/drivers/staging/tidspbridge/include/dspbridge/cmm.h

@@ -81,7 +81,7 @@ extern void *cmm_calloc_buf(struct cmm_object *hcmm_mgr,
  *  Requires:
  *      cmm_init(void) called.
  *      ph_cmm_mgr != NULL.
- *      mgr_attrts->ul_min_block_size >= 4 bytes.
+ *      mgr_attrts->min_block_size >= 4 bytes.
  *  Ensures:
  *
  */

trunk/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h

@@ -23,13 +23,13 @@
 /* Cmm attributes used in cmm_create() */
 struct cmm_mgrattrs {
 	/* Minimum SM allocation; default 32 bytes. */
-	u32 ul_min_block_size;
+	u32 min_block_size;
 };
 
 /* Attributes for CMM_AllocBuf() & CMM_AllocDesc() */
 struct cmm_attrs {
 	u32 ul_seg_id;		/*  1,2... are SM segments. 0 is not. */
-	u32 alignment;		/*  0,1,2,4....ul_min_block_size */
+	u32 alignment;		/*  0,1,2,4....min_block_size */
 };
 
 /*
@@ -55,23 +55,23 @@ struct cmm_seginfo {
 	/* Total size in bytes of segment: DSP+GPP */
 	u32 ul_total_seg_size;
 	u32 gpp_base_pa;	/* Start Phys addr of Gpp SM seg */
-	u32 ul_gpp_size;	/* Size of Gpp SM seg in bytes */
+	u32 gpp_size;	/* Size of Gpp SM seg in bytes */
 	u32 dsp_base_va;	/* DSP virt base byte address */
 	u32 dsp_size;		/* DSP seg size in bytes */
 	/* # of current GPP allocations from this segment */
-	u32 ul_in_use_cnt;
+	u32 in_use_cnt;
 	u32 seg_base_va;	/* Start Virt address of SM seg */
 
 };
 
 /* CMM useful information */
 struct cmm_info {
 	/* # of SM segments registered with this Cmm. */
-	u32 ul_num_gppsm_segs;
+	u32 num_gppsm_segs;
 	/* Total # of allocations outstanding for CMM */
 	u32 ul_total_in_use_cnt;
 	/* Min SM block size allocation from cmm_create() */
-	u32 ul_min_block_size;
+	u32 min_block_size;
 	/* Info per registered SM segment. */
 	struct cmm_seginfo seg_info[CMM_MAXGPPSEGS];
 };

trunk/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h

@@ -210,9 +210,9 @@ enum dsp_flushtype {
 struct dsp_memstat {
 	u32 ul_size;
 	u32 ul_total_free_size;
-	u32 ul_len_max_free_block;
-	u32 ul_num_free_blocks;
-	u32 ul_num_alloc_blocks;
+	u32 len_max_free_block;
+	u32 num_free_blocks;
+	u32 num_alloc_blocks;
 };
 
 /* Processor Load information Values */
@@ -276,7 +276,7 @@ struct dsp_streamconnect {
 };
 
 struct dsp_nodeprofs {
-	u32 ul_heap_size;
+	u32 heap_size;
 };
 
 /* The dsp_ndbprops structure reports the attributes of a node */
@@ -358,7 +358,7 @@ struct dsp_processorinfo {
 	int processor_family;
 	int processor_type;
 	u32 clock_rate;
-	u32 ul_internal_mem_size;
+	u32 internal_mem_size;
 	u32 external_mem_size;
 	u32 processor_id;
 	int ty_running_rtos;
@@ -425,7 +425,7 @@ struct dsp_streaminfo {
 	u32 cb_struct;
 	u32 number_bufs_allowed;
 	u32 number_bufs_in_stream;
-	u32 ul_number_bytes;
+	u32 number_bytes;
 	void *sync_object_handle;
 	enum dsp_streamstate ss_stream_state;
 };

trunk/drivers/staging/tidspbridge/include/dspbridge/dspioctl.h

@@ -58,7 +58,7 @@ struct bridge_ioctl_extproc {
 	u32 dsp_va;		/* DSP virtual address */
 	u32 gpp_pa;		/* GPP physical address */
 	/* GPP virtual address. __va does not work for ioremapped addresses */
-	u32 ul_gpp_va;
+	u32 gpp_va;
 	u32 ul_size;		/* Size of the mapped memory in bytes */
 	enum hw_endianism_t endianism;
 	enum hw_mmu_mixed_size_t mixed_mode;

trunk/drivers/staging/tidspbridge/include/dspbridge/mgrpriv.h

@@ -29,7 +29,7 @@ struct mgr_object;
 
 struct mgr_tlbentry {
 	u32 dsp_virt;	/* DSP virtual address */
-	u32 ul_gpp_phys;	/* GPP physical address */
+	u32 gpp_phys;	/* GPP physical address */
 };
 
 /*