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yaml
---
r: 196204
b: refs/heads/master
c: 2a9f5a4
h: refs/heads/master
v: v3
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Paul Walmsley committed May 20, 2010
1 parent b454502 commit f90c8b6
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Showing 2 changed files with 37 additions and 128 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 63405360fc8973d28e1c7c0f8e0fc77338a6ce23
refs/heads/master: 2a9f5a4d455aa88a03dac1dca8f686e3c21fc1b2
163 changes: 36 additions & 127 deletions trunk/arch/arm/mach-omap2/clock3xxx_data.c
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Expand Up @@ -232,23 +232,23 @@ static const struct clksel_rate div16_dpll_rates[] = {
{ .div = 0 }
};

static const struct clksel_rate div32_dpll4_rates_3630[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_36XX },
{ .div = 2, .val = 2, .flags = RATE_IN_36XX },
{ .div = 3, .val = 3, .flags = RATE_IN_36XX },
{ .div = 4, .val = 4, .flags = RATE_IN_36XX },
{ .div = 5, .val = 5, .flags = RATE_IN_36XX },
{ .div = 6, .val = 6, .flags = RATE_IN_36XX },
{ .div = 7, .val = 7, .flags = RATE_IN_36XX },
{ .div = 8, .val = 8, .flags = RATE_IN_36XX },
{ .div = 9, .val = 9, .flags = RATE_IN_36XX },
{ .div = 10, .val = 10, .flags = RATE_IN_36XX },
{ .div = 11, .val = 11, .flags = RATE_IN_36XX },
{ .div = 12, .val = 12, .flags = RATE_IN_36XX },
{ .div = 13, .val = 13, .flags = RATE_IN_36XX },
{ .div = 14, .val = 14, .flags = RATE_IN_36XX },
{ .div = 15, .val = 15, .flags = RATE_IN_36XX },
{ .div = 16, .val = 16, .flags = RATE_IN_36XX },
static const struct clksel_rate dpll4_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
{ .div = 17, .val = 17, .flags = RATE_IN_36XX },
{ .div = 18, .val = 18, .flags = RATE_IN_36XX },
{ .div = 19, .val = 19, .flags = RATE_IN_36XX },
Expand Down Expand Up @@ -562,6 +562,7 @@ static struct clk emu_core_alwon_ck = {
/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
/* Type: DPLL */
static struct dpll_data dpll4_dd;

static struct dpll_data dpll4_dd_34xx __initdata = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
.mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
Expand Down Expand Up @@ -632,39 +633,20 @@ static struct clk dpll4_x2_ck = {
.recalc = &omap3_clkoutx2_recalc,
};

static const struct clksel div16_dpll4_clksel[] = {
{ .parent = &dpll4_ck, .rates = div16_dpll_rates },
{ .parent = NULL }
};

static const struct clksel div32_dpll4_clksel[] = {
{ .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
static const struct clksel dpll4_clksel[] = {
{ .parent = &dpll4_ck, .rates = dpll4_rates },
{ .parent = NULL }
};

/* This virtual clock is the source for dpll4_m2x2_ck */
static struct clk dpll4_m2_ck;

static struct clk dpll4_m2_ck_34xx __initdata = {
.name = "dpll4_m2_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
.clksel_mask = OMAP3430_DIV_96M_MASK,
.clksel = div16_dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};

static struct clk dpll4_m2_ck_3630 __initdata = {
static struct clk dpll4_m2_ck = {
.name = "dpll4_m2_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
.clksel_mask = OMAP3630_DIV_96M_MASK,
.clksel = div32_dpll4_clksel,
.clksel = dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};
Expand Down Expand Up @@ -760,28 +742,14 @@ static struct clk omap_96m_fck = {
};

/* This virtual clock is the source for dpll4_m3x2_ck */
static struct clk dpll4_m3_ck;

static struct clk dpll4_m3_ck_34xx __initdata = {
static struct clk dpll4_m3_ck = {
.name = "dpll4_m3_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_TV_MASK,
.clksel = div16_dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};

static struct clk dpll4_m3_ck_3630 __initdata = {
.name = "dpll4_m3_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3630_CLKSEL_TV_MASK,
.clksel = div32_dpll4_clksel,
.clksel = dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};
Expand Down Expand Up @@ -858,31 +826,15 @@ static struct clk omap_12m_fck = {
.recalc = &omap_fixed_divisor_recalc,
};

/* This virstual clock is the source for dpll4_m4x2_ck */
static struct clk dpll4_m4_ck;

static struct clk dpll4_m4_ck_34xx __initdata = {
/* This virtual clock is the source for dpll4_m4x2_ck */
static struct clk dpll4_m4_ck = {
.name = "dpll4_m4_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
.clksel = div16_dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
};

static struct clk dpll4_m4_ck_3630 __initdata = {
.name = "dpll4_m4_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
.clksel = div32_dpll4_clksel,
.clksel = dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
.set_rate = &omap2_clksel_set_rate,
Expand All @@ -902,30 +854,14 @@ static struct clk dpll4_m4x2_ck = {
};

/* This virtual clock is the source for dpll4_m5x2_ck */
static struct clk dpll4_m5_ck;

static struct clk dpll4_m5_ck_34xx __initdata = {
static struct clk dpll4_m5_ck = {
.name = "dpll4_m5_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
.clksel = div16_dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
.recalc = &omap2_clksel_recalc,
};

static struct clk dpll4_m5_ck_3630 __initdata = {
.name = "dpll4_m5_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
.clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
.clksel = div32_dpll4_clksel,
.clksel = dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
Expand All @@ -945,28 +881,14 @@ static struct clk dpll4_m5x2_ck = {
};

/* This virtual clock is the source for dpll4_m6x2_ck */
static struct clk dpll4_m6_ck;

static struct clk dpll4_m6_ck_34xx __initdata = {
static struct clk dpll4_m6_ck = {
.name = "dpll4_m6_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_DIV_DPLL4_MASK,
.clksel = div16_dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};

static struct clk dpll4_m6_ck_3630 __initdata = {
.name = "dpll4_m6_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3630_DIV_DPLL4_MASK,
.clksel = div32_dpll4_clksel,
.clksel = dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};
Expand Down Expand Up @@ -3521,14 +3443,7 @@ int __init omap3xxx_clk_init(void)
/*
* XXX This type of dynamic rewriting of the clock tree is
* deprecated and should be revised soon.
*/
dpll4_m2_ck = dpll4_m2_ck_3630;
dpll4_m3_ck = dpll4_m3_ck_3630;
dpll4_m4_ck = dpll4_m4_ck_3630;
dpll4_m5_ck = dpll4_m5_ck_3630;
dpll4_m6_ck = dpll4_m6_ck_3630;

/*
*
* For 3630: override clkops_omap2_dflt_wait for the
* clocks affected from PWRDN reset Limitation
*/
Expand All @@ -3544,18 +3459,12 @@ int __init omap3xxx_clk_init(void)
&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
dpll4_m6x2_ck.ops =
&clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
} else {
/*
* XXX This type of dynamic rewriting of the clock tree is
* deprecated and should be revised soon.
*/
dpll4_m2_ck = dpll4_m2_ck_34xx;
dpll4_m3_ck = dpll4_m3_ck_34xx;
dpll4_m4_ck = dpll4_m4_ck_34xx;
dpll4_m5_ck = dpll4_m5_ck_34xx;
dpll4_m6_ck = dpll4_m6_ck_34xx;
}

/*
* XXX This type of dynamic rewriting of the clock tree is
* deprecated and should be revised soon.
*/
if (cpu_is_omap3630())
dpll4_dd = dpll4_dd_3630;
else
Expand Down

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