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yaml
---
r: 292421
b: refs/heads/master
c: 69d23b6
h: refs/heads/master
i:
  292419: 045bb52
v: v3
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Greg Ungerer committed Mar 4, 2012
1 parent 3add50f commit f94569d
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Showing 3 changed files with 11 additions and 9 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 35b7cf22c6b2481f7c425f30898214f73376834d
refs/heads/master: 69d23b610a04e269d6a094e6f3e37d85d6b2784a
6 changes: 4 additions & 2 deletions trunk/arch/m68k/include/asm/m5407sim.h
Original file line number Diff line number Diff line change
Expand Up @@ -85,8 +85,8 @@
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */

#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */

#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
Expand Down Expand Up @@ -139,6 +139,8 @@
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */

/****************************************************************************/
#endif /* m5407sim_h */
12 changes: 6 additions & 6 deletions trunk/arch/m68k/platform/5407/config.c
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Expand Up @@ -22,12 +22,12 @@

static struct mcf_platform_uart m5407_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.irq = 73,
.mapbase = MCFUART_BASE0,
.irq = MCF_IRQ_UART0,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.irq = 74,
.mapbase = MCFUART_BASE1,
.irq = MCF_IRQ_UART1,
},
{ },
};
Expand All @@ -48,11 +48,11 @@ static void __init m5407_uart_init_line(int line, int irq)
{
if (line == 0) {
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
writeb(irq, MCFUART_BASE0 + MCFUART_UIVR);
mcf_mapirq2imr(irq, MCFINTC_UART0);
} else if (line == 1) {
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
mcf_mapirq2imr(irq, MCFINTC_UART1);
}
}
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