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yaml
---
r: 278151
b: refs/heads/master
c: db54eb5
h: refs/heads/master
i:
  278149: 1a0f673
  278147: bc21bd2
  278143: b42e3c2
v: v3
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Stanislaw Gruszka committed Nov 15, 2011
1 parent b764cb1 commit f99810b
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Showing 8 changed files with 73 additions and 72 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 0c1a94e299eed7ea11ebc407d1e08a26c594abe5
refs/heads/master: db54eb57ce5edeebd621b12e23f3e1cdea7fe3ee
48 changes: 24 additions & 24 deletions trunk/drivers/net/wireless/iwlegacy/iwl-3945.c
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Original file line number Diff line number Diff line change
Expand Up @@ -797,18 +797,18 @@ static int il3945_tx_reset(struct il_priv *il)
{

/* bypass mode */
il_write_prph(il, ALM_SCD_MODE_REG, 0x2);
il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);

/* RA 0 is active */
il_write_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);

/* all 6 fifo are active */
il_write_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);

il_write_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
il_write_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
il_write_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
il_write_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);

il_wr(il, FH39_TSSR_CBB_BASE,
il->_3945.shared_phys);
Expand Down Expand Up @@ -878,8 +878,8 @@ static int il3945_apm_init(struct il_priv *il)
int ret = il_apm_init(il);

/* Clear APMG (NIC's internal power management) interrupts */
il_write_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
il_write_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);

/* Reset radio chip */
il_set_bits_prph(il, APMG_PS_CTRL_REG,
Expand Down Expand Up @@ -1025,8 +1025,8 @@ void il3945_hw_txq_ctx_stop(struct il_priv *il)
int txq_id;

/* stop SCD */
il_write_prph(il, ALM_SCD_MODE_REG, 0);
il_write_prph(il, ALM_SCD_TXFACT_REG, 0);
il_wr_prph(il, ALM_SCD_MODE_REG, 0);
il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);

/* reset TFD queues */
for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
Expand Down Expand Up @@ -2475,11 +2475,11 @@ static int il3945_verify_bsm(struct il_priv *il)
D_INFO("Begin verify bsm\n");

/* verify BSM SRAM contents */
val = il_read_prph(il, BSM_WR_DWCOUNT_REG);
val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
for (reg = BSM_SRAM_LOWER_BOUND;
reg < BSM_SRAM_LOWER_BOUND + len;
reg += sizeof(u32), image++) {
val = il_read_prph(il, reg);
val = il_rd_prph(il, reg);
if (val != le32_to_cpu(*image)) {
IL_ERR("BSM uCode verification failed at "
"addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
Expand Down Expand Up @@ -2583,36 +2583,36 @@ static int il3945_load_bsm(struct il_priv *il)
inst_len = il->ucode_init.len;
data_len = il->ucode_init_data.len;

il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);

/* Fill BSM memory with bootstrap instructions */
for (reg_offset = BSM_SRAM_LOWER_BOUND;
reg_offset < BSM_SRAM_LOWER_BOUND + len;
reg_offset += sizeof(u32), image++)
_il_write_prph(il, reg_offset,
_il_wr_prph(il, reg_offset,
le32_to_cpu(*image));

rc = il3945_verify_bsm(il);
if (rc)
return rc;

/* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
il_write_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
il_write_prph(il, BSM_WR_MEM_DST_REG,
il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
il_wr_prph(il, BSM_WR_MEM_DST_REG,
IWL39_RTC_INST_LOWER_BOUND);
il_write_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));

/* Load bootstrap code into instruction SRAM now,
* to prepare to load "initialize" uCode */
il_write_prph(il, BSM_WR_CTRL_REG,
il_wr_prph(il, BSM_WR_CTRL_REG,
BSM_WR_CTRL_REG_BIT_START);

/* Wait for load of bootstrap uCode to finish */
for (i = 0; i < 100; i++) {
done = il_read_prph(il, BSM_WR_CTRL_REG);
done = il_rd_prph(il, BSM_WR_CTRL_REG);
if (!(done & BSM_WR_CTRL_REG_BIT_START))
break;
udelay(10);
Expand All @@ -2626,7 +2626,7 @@ static int il3945_load_bsm(struct il_priv *il)

/* Enable future boot loads whenever power management unit triggers it
* (e.g. when powering back up after power-save shutdown) */
il_write_prph(il, BSM_WR_CTRL_REG,
il_wr_prph(il, BSM_WR_CTRL_REG,
BSM_WR_CTRL_REG_BIT_START_EN);

return 0;
Expand Down
2 changes: 1 addition & 1 deletion trunk/drivers/net/wireless/iwlegacy/iwl-4965-tx.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -754,7 +754,7 @@ static void il4965_tx_queue_stop_scheduler(struct il_priv *il,
{
/* Simply stop the queue, but don't change any configuration;
* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
il_write_prph(il,
il_wr_prph(il,
IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
(0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
(1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
Expand Down
34 changes: 17 additions & 17 deletions trunk/drivers/net/wireless/iwlegacy/iwl-4965.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,11 +72,11 @@ static int il4965_verify_bsm(struct il_priv *il)
D_INFO("Begin verify bsm\n");

/* verify BSM SRAM contents */
val = il_read_prph(il, BSM_WR_DWCOUNT_REG);
val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
for (reg = BSM_SRAM_LOWER_BOUND;
reg < BSM_SRAM_LOWER_BOUND + len;
reg += sizeof(u32), image++) {
val = il_read_prph(il, reg);
val = il_rd_prph(il, reg);
if (val != le32_to_cpu(*image)) {
IL_ERR("BSM uCode verification failed at "
"addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
Expand Down Expand Up @@ -156,34 +156,34 @@ static int il4965_load_bsm(struct il_priv *il)
inst_len = il->ucode_init.len;
data_len = il->ucode_init_data.len;

il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);

/* Fill BSM memory with bootstrap instructions */
for (reg_offset = BSM_SRAM_LOWER_BOUND;
reg_offset < BSM_SRAM_LOWER_BOUND + len;
reg_offset += sizeof(u32), image++)
_il_write_prph(il, reg_offset, le32_to_cpu(*image));
_il_wr_prph(il, reg_offset, le32_to_cpu(*image));

ret = il4965_verify_bsm(il);
if (ret)
return ret;

/* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
il_write_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
il_write_prph(il,
il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
il_wr_prph(il,
BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
il_write_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));

/* Load bootstrap code into instruction SRAM now,
* to prepare to load "initialize" uCode */
il_write_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);

/* Wait for load of bootstrap uCode to finish */
for (i = 0; i < 100; i++) {
done = il_read_prph(il, BSM_WR_CTRL_REG);
done = il_rd_prph(il, BSM_WR_CTRL_REG);
if (!(done & BSM_WR_CTRL_REG_BIT_START))
break;
udelay(10);
Expand All @@ -197,7 +197,7 @@ static int il4965_load_bsm(struct il_priv *il)

/* Enable future boot loads whenever power management unit triggers it
* (e.g. when powering back up after power-save shutdown) */
il_write_prph(il,
il_wr_prph(il,
BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);


Expand All @@ -224,14 +224,14 @@ static int il4965_set_ucode_ptrs(struct il_priv *il)
pdata = il->ucode_data_backup.p_addr >> 4;

/* Tell bootstrap uCode where to find image to load */
il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
il->ucode_data.len);

/* Inst byte count must be last to set up, bit 31 signals uCode
* that all new ptr/size info is in place */
il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
il->ucode_code.len | BSM_DRAM_INST_LOAD);
D_INFO("Runtime uCode pointers are set.\n");

Expand Down
6 changes: 3 additions & 3 deletions trunk/drivers/net/wireless/iwlegacy/iwl-core.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1069,7 +1069,7 @@ int il_apm_init(struct il_priv *il)

/*
* Wait for clock stabilization; once stabilized, access to
* device-internal resources is supported, e.g. il_write_prph()
* device-internal resources is supported, e.g. il_wr_prph()
* and accesses to uCode SRAM.
*/
ret = _il_poll_bit(il, CSR_GP_CNTRL,
Expand All @@ -1089,10 +1089,10 @@ int il_apm_init(struct il_priv *il)
* set by default in "CLK_CTRL_REG" after reset.
*/
if (il->cfg->base_params->use_bsm)
il_write_prph(il, APMG_CLK_EN_REG,
il_wr_prph(il, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
else
il_write_prph(il, APMG_CLK_EN_REG,
il_wr_prph(il, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT);
udelay(20);

Expand Down
23 changes: 12 additions & 11 deletions trunk/drivers/net/wireless/iwlegacy/iwl-io.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -197,26 +197,27 @@ static inline int il_poll_bit(struct il_priv *il, u32 addr,
return -ETIMEDOUT;
}

static inline u32 _il_read_prph(struct il_priv *il, u32 reg)
static inline u32 _il_rd_prph(struct il_priv *il, u32 reg)
{
_il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
rmb();
return _il_rd(il, HBUS_TARG_PRPH_RDAT);
}
static inline u32 il_read_prph(struct il_priv *il, u32 reg)

static inline u32 il_rd_prph(struct il_priv *il, u32 reg)
{
unsigned long reg_flags;
u32 val;

spin_lock_irqsave(&il->reg_lock, reg_flags);
_il_grab_nic_access(il);
val = _il_read_prph(il, reg);
val = _il_rd_prph(il, reg);
_il_release_nic_access(il);
spin_unlock_irqrestore(&il->reg_lock, reg_flags);
return val;
}

static inline void _il_write_prph(struct il_priv *il,
static inline void _il_wr_prph(struct il_priv *il,
u32 addr, u32 val)
{
_il_wr(il, HBUS_TARG_PRPH_WADDR,
Expand All @@ -226,20 +227,20 @@ static inline void _il_write_prph(struct il_priv *il,
}

static inline void
il_write_prph(struct il_priv *il, u32 addr, u32 val)
il_wr_prph(struct il_priv *il, u32 addr, u32 val)
{
unsigned long reg_flags;

spin_lock_irqsave(&il->reg_lock, reg_flags);
if (!_il_grab_nic_access(il)) {
_il_write_prph(il, addr, val);
_il_wr_prph(il, addr, val);
_il_release_nic_access(il);
}
spin_unlock_irqrestore(&il->reg_lock, reg_flags);
}

#define _il_set_bits_prph(il, reg, mask) \
_il_write_prph(il, reg, (_il_read_prph(il, reg) | mask))
_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask))

static inline void
il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
Expand All @@ -254,8 +255,8 @@ il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
}

#define _il_set_bits_mask_prph(il, reg, bits, mask) \
_il_write_prph(il, reg, \
((_il_read_prph(il, reg) & mask) | bits))
_il_wr_prph(il, reg, \
((_il_rd_prph(il, reg) & mask) | bits))

static inline void il_set_bits_mask_prph(struct il_priv *il, u32 reg,
u32 bits, u32 mask)
Expand All @@ -277,8 +278,8 @@ static inline void il_clear_bits_prph(struct il_priv

spin_lock_irqsave(&il->reg_lock, reg_flags);
_il_grab_nic_access(il);
val = _il_read_prph(il, reg);
_il_write_prph(il, reg, (val & ~mask));
val = _il_rd_prph(il, reg);
_il_wr_prph(il, reg, (val & ~mask));
_il_release_nic_access(il);
spin_unlock_irqrestore(&il->reg_lock, reg_flags);
}
Expand Down
12 changes: 6 additions & 6 deletions trunk/drivers/net/wireless/iwlegacy/iwl3945-base.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2122,14 +2122,14 @@ static int il3945_set_ucode_ptrs(struct il_priv *il)
pdata = il->ucode_data_backup.p_addr;

/* Tell bootstrap uCode where to find image to load */
il_write_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_write_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_write_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG,
il->ucode_data.len);

/* Inst byte count must be last to set up, bit 31 signals uCode
* that all new ptr/size info is in place */
il_write_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
il->ucode_code.len | BSM_DRAM_INST_LOAD);

D_INFO("Runtime uCode pointers are set.\n");
Expand Down Expand Up @@ -2210,7 +2210,7 @@ static void il3945_alive_start(struct il_priv *il)
goto restart;
}

rfkill = il_read_prph(il, APMG_RFKILL_REG);
rfkill = il_rd_prph(il, APMG_RFKILL_REG);
D_INFO("RFKILL status: 0x%x\n", rfkill);

if (rfkill & 0x1) {
Expand Down Expand Up @@ -2342,7 +2342,7 @@ static void __il3945_down(struct il_priv *il)
il3945_hw_rxq_stop(il);

/* Power-down device's busmaster DMA clocks */
il_write_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
udelay(5);

/* Stop the device, and put it in low power state */
Expand Down
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