---

yaml --- r: 115723 b: refs/heads/master c: 0cdad7e h: refs/heads/master i: 115721: b5ac4be 115719: 0556915 v: v3
git-mirror · Oct 17, 2008 · fa6ed52 · fa6ed52
1 parent 871e2a2
commit fa6ed52
Show file tree

Hide file tree

Showing 2 changed files with 9 additions and 7 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 630681d9a5314e6cf53d144f7f58b7c19862a7d3
+refs/heads/master: 0cdad7e88a23910a911a3339ff2d70f8f952d7b8
diff --git a/trunk/drivers/gpu/drm/i915/i915_drv.h b/trunk/drivers/gpu/drm/i915/i915_drv.h
@@ -597,16 +597,18 @@ extern void opregion_enable_asle(struct drm_device *dev);
  * MI_STORE_DATA_IMM.
  *
  * The following dwords have a reserved meaning:
- * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
- * 4: ring 0 head pointer
- * 5: ring 1 head pointer (915-class)
- * 6: ring 2 head pointer (915-class)
+ * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
+ * 0x04: ring 0 head pointer
+ * 0x05: ring 1 head pointer (915-class)
+ * 0x06: ring 2 head pointer (915-class)
+ * 0x10-0x1b: Context status DWords (GM45)
+ * 0x1f: Last written status offset. (GM45)
  *
- * The area from dword 0x10 to 0x3ff is available for driver usage.
+ * The area from dword 0x20 to 0x3ff is available for driver usage.
  */
 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
-#define I915_GEM_HWS_INDEX		0x10
+#define I915_GEM_HWS_INDEX		0x20
 
 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);