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yaml
---
r: 205872
b: refs/heads/master
c: 7124cb1
h: refs/heads/master
v: v3
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Nishanth Menon authored and Greg Kroah-Hartman committed Jul 22, 2010
1 parent 167bd10 commit fb5b6f1
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Showing 5 changed files with 45 additions and 107 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 2094f12d440c5a9fae032932266fa4a44135194c
refs/heads/master: 7124cb171108dea386b2c81334605da1d6f4554a
18 changes: 6 additions & 12 deletions trunk/drivers/staging/tidspbridge/core/tiomap3430.c
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Original file line number Diff line number Diff line change
Expand Up @@ -555,24 +555,18 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg;

/*PM_IVA2GRPSEL_PER = 0xC0;*/
temp = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) + 0xA8));
temp = readl(resources->dw_per_pm_base + 0xA8);
temp = (temp & 0xFFFFFF30) | 0xC0;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) =
(u32) temp;
writel(temp, resources->dw_per_pm_base + 0xA8);

/*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
temp = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) + 0xA4));
temp = readl(resources->dw_per_pm_base + 0xA4);
temp = (temp & 0xFFFFFF3F);
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) =
(u32) temp;
writel(temp, resources->dw_per_pm_base + 0xA4);
/*CM_SLEEPDEP_PER |= 0x04; */
temp = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_base) + 0x44));
temp = readl(resources->dw_per_base + 0x44);
temp = (temp & 0xFFFFFFFB) | 0x04;
*((reg_uword32 *) ((u32) (resources->dw_per_base) + 0x44)) =
(u32) temp;
writel(temp, resources->dw_per_base + 0x44);

/*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
(*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
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126 changes: 36 additions & 90 deletions trunk/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
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Original file line number Diff line number Diff line change
Expand Up @@ -430,175 +430,121 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)

switch (clock_id) {
case BPWR_GP_TIMER5:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER6:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER7:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER8:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP1:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_core_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_core_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4);
break;
case BPWR_MCBSP2:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP3:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP4:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP5:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_core_pm_base) +
0xA8));
mpu_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_core_pm_base) +
0xA4));
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
}
*((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8))
= iva2_grpsel;
*((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4))
= mpu_grpsel;
writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
}
}
2 changes: 1 addition & 1 deletion trunk/drivers/staging/tidspbridge/core/tiomap_io.c
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Original file line number Diff line number Diff line change
Expand Up @@ -439,7 +439,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
omap_mbox_restore_ctx(dev_context->mbox);

/* Access MMU SYS CONFIG register to generate a short wakeup */
temp = *(reg_uword32 *) (resources->dw_dmmu_base + 0x10);
temp = readl(resources->dw_dmmu_base + 0x10);

dev_context->dw_brd_state = BRD_RUNNING;
} else if (dev_context->dw_brd_state == BRD_RETENTION) {
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4 changes: 1 addition & 3 deletions trunk/drivers/staging/tidspbridge/rmgr/node.c
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Original file line number Diff line number Diff line change
Expand Up @@ -623,9 +623,7 @@ int node_allocate(struct proc_object *hprocessor,
ul_gpp_mem_base = (u32) host_res->dw_mem_base[1];
off_set = pul_value - dynext_base;
ul_stack_seg_addr = ul_gpp_mem_base + off_set;
ul_stack_seg_val = (u32) *((reg_uword32 *)
((u32)
(ul_stack_seg_addr)));
ul_stack_seg_val = readl(ul_stack_seg_addr);

dev_dbg(bridge, "%s: StackSegVal = 0x%x, StackSegAddr ="
" 0x%x\n", __func__, ul_stack_seg_val,
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