---

yaml
---
r: 173123
b: refs/heads/master
c: 39fe05e
h: refs/heads/master
i:
  173121: bec49b2
  173119: ec6fb4d
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e069efb6bbf8f739a2e084183709b5eb76abf90d
+refs/heads/master: 39fe05e58c5e448601ce46e6b03900d5bf31c4b0

trunk/.gitignore

@@ -25,7 +25,6 @@
 *.elf
 *.bin
 *.gz
-*.bz2
 *.lzma
 *.patch
 *.gcno

trunk/CREDITS

@@ -2800,7 +2800,7 @@ D: Starter of Linux1394 effort
 S: ask per mail for current address
 
 N: Nicolas Pitre
-E: nico@fluxnic.net
+E: nico@cam.org
 D: StrongARM SA1100 support integrator & hacker
 D: Xscale PXA architecture
 D: unified SMC 91C9x/91C11x ethernet driver (smc91x)

trunk/Documentation/00-INDEX

@@ -82,8 +82,6 @@ block/
 	- info on the Block I/O (BIO) layer.
 blockdev/
 	- info on block devices & drivers
-btmrvl.txt
-	- info on Marvell Bluetooth driver usage.
 cachetlb.txt
 	- describes the cache/TLB flushing interfaces Linux uses.
 cdrom/

trunk/Documentation/ABI/testing/sysfs-bus-pci

@@ -84,16 +84,6 @@ Description:
 		from this part of the device tree.
 		Depends on CONFIG_HOTPLUG.
 
-What:		/sys/bus/pci/devices/.../reset
-Date:		July 2009
-Contact:	Michael S. Tsirkin <mst@redhat.com>
-Description:
-		Some devices allow an individual function to be reset
-		without affecting other functions in the same device.
-		For devices that have this support, a file named reset
-		will be present in sysfs.  Writing 1 to this file
-		will perform reset.
-
 What:		/sys/bus/pci/devices/.../vpd
 Date:		February 2008
 Contact:	Ben Hutchings <bhutchings@solarflare.com>

trunk/Documentation/ABI/testing/sysfs-bus-pci-devices-cciss

@@ -31,31 +31,3 @@ Date:		March 2009
 Kernel Version: 2.6.30
 Contact:	iss_storagedev@hp.com
 Description:	A symbolic link to /sys/block/cciss!cXdY
-
-Where:		/sys/bus/pci/devices/<dev>/ccissX/rescan
-Date:		August 2009
-Kernel Version:	2.6.31
-Contact:	iss_storagedev@hp.com
-Description:	Kicks of a rescan of the controller to discover logical
-		drive topology changes.
-
-Where:		/sys/bus/pci/devices/<dev>/ccissX/cXdY/lunid
-Date:		August 2009
-Kernel Version: 2.6.31
-Contact:	iss_storagedev@hp.com
-Description:	Displays the 8-byte LUN ID used to address logical
-		drive Y of controller X.
-
-Where:		/sys/bus/pci/devices/<dev>/ccissX/cXdY/raid_level
-Date:		August 2009
-Kernel Version: 2.6.31
-Contact:	iss_storagedev@hp.com
-Description:	Displays the RAID level of logical drive Y of
-		controller X.
-
-Where:		/sys/bus/pci/devices/<dev>/ccissX/cXdY/usage_count
-Date:		August 2009
-Kernel Version: 2.6.31
-Contact:	iss_storagedev@hp.com
-Description:	Displays the usage count (number of opens) of logical drive Y
-		of controller X.

trunk/Documentation/ABI/testing/sysfs-class-usb_host

@@ -0,0 +1,25 @@
+What:           /sys/class/usb_host/usb_hostN/wusb_chid
+Date:           July 2008
+KernelVersion:  2.6.27
+Contact:        David Vrabel <david.vrabel@csr.com>
+Description:
+                Write the CHID (16 space-separated hex octets) for this host controller.
+                This starts the host controller, allowing it to accept connection from
+                WUSB devices.
+
+                Set an all zero CHID to stop the host controller.
+
+What:           /sys/class/usb_host/usb_hostN/wusb_trust_timeout
+Date:           July 2008
+KernelVersion:  2.6.27
+Contact:        David Vrabel <david.vrabel@csr.com>
+Description:
+                Devices that haven't sent a WUSB packet to the host
+                within 'wusb_trust_timeout' ms are considered to have
+                disconnected and are removed.  The default value of
+                4000 ms is the value required by the WUSB
+                specification.
+
+                Since this relates to security (specifically, the
+                lifetime of PTKs and GTKs) it should not be changed
+                from the default.

trunk/Documentation/ABI/testing/sysfs-devices-cache_disable

@@ -0,0 +1,18 @@
+What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
+Date:      August 2008
+KernelVersion:	2.6.27
+Contact:	mark.langsdorf@amd.com
+Description:	These files exist in every cpu's cache index directories.
+		There are currently 2 cache_disable_# files in each
+		directory.  Reading from these files on a supported
+		processor will return that cache disable index value
+		for that processor and node.  Writing to one of these
+		files will cause the specificed cache index to be disabled.
+
+		Currently, only AMD Family 10h Processors support cache index
+		disable, and only for their L3 caches.  See the BIOS and
+		Kernel Developer's Guide at
+		http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
+		for formatting information and other details on the
+		cache index disable.
+Users:    joachim.deguara@amd.com