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powerpc/85xx: Use fsl,mpc85.. as prefix for memory ctrl & l2-cache nodes
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Older devices tree's used "fsl,85.." instead of the preferred
"fsl,mpc85.." for the memory controller & l2 cache controller nodes.
The EDAC code is the only use of these and has been updated for some
time to support both "fsl,85.." and "fsl,mpc85.."

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala committed Mar 31, 2009
1 parent 9310933 commit fe67177
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Showing 8 changed files with 16 additions and 16 deletions.
4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/ksi8560.dts
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Expand Up @@ -57,14 +57,14 @@
bus-frequency = <0>; /* Fixed by bootwrapper */

memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <0x12 0x2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; /* 32 bytes */
cache-size = <0x40000>; /* L2, 256K */
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4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/sbc8548.dts
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Expand Up @@ -156,14 +156,14 @@
compatible = "simple-bus";

memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
compatible = "fsl,mpc8548-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <0x12 0x2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
compatible = "fsl,mpc8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
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4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/sbc8560.dts
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Expand Up @@ -61,14 +61,14 @@
clock-frequency = <0>;

memory-controller@2000 {
compatible = "fsl,8560-memory-controller";
compatible = "fsl,mpc8560-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <0x12 0x2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8560-l2-cache-controller";
compatible = "fsl,mpc8560-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
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4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/stx_gp3_8560.dts
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Expand Up @@ -57,14 +57,14 @@
compatible = "fsl,mpc8560-immr", "simple-bus";

memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
cache-size = <0x40000>; // L2, 256K
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4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/tqm8540.dts
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Expand Up @@ -59,14 +59,14 @@
compatible = "fsl,mpc8540-immr", "simple-bus";

memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
cache-size = <0x40000>; // L2, 256K
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4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/tqm8541.dts
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Expand Up @@ -58,14 +58,14 @@
compatible = "fsl,mpc8541-immr", "simple-bus";

memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
cache-size = <0x40000>; // L2, 256K
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4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/tqm8555.dts
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Expand Up @@ -58,14 +58,14 @@
compatible = "fsl,mpc8555-immr", "simple-bus";

memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
cache-size = <0x40000>; // L2, 256K
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4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/tqm8560.dts
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Expand Up @@ -60,14 +60,14 @@
compatible = "fsl,mpc8560-immr", "simple-bus";

memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
compatible = "fsl,mpc8540-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};

L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
compatible = "fsl,mpc8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
cache-size = <0x40000>; // L2, 256K
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