Skip to content

Commit

Permalink
Merge tag 'qcom-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/ke…
Browse files Browse the repository at this point in the history
…rnel/git/galak/linux-qcom into next/dt

Merge "qcom DT changes for v3.18" from Kumar Gala:

Qualcomm ARM Based Device Tree Updates for v3.18

* Added APQ8084 dt support for clocks, serial, pinctrl, and IFC6540 board
* Added IPQ8064 dt support for basic SoC and AP148 board
* Added APQ8064 dt support for pinctrl, reset, SDHC, and multimedia clocks
* Added PMIC 8058 dt support on MSM8660, enables PMIC based power key,
  keypad, rtc, and vibrator
* Added PMIC 8921 dt support on MSM8960, enables PMIC based power key,
  keypad, and rtc

* tag 'qcom-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
  ARM: DT: QCOM: apq8064: Add dma support for sdcc node
  ARM: DT: apq8064: Add sdcc support via mcci driver.
  ARM: dts: qcom: Add 8064 multimedia clock controller node
  ARM: DT: APQ8064: Add node for ps_hold function in pinctrl
  ARM: DT: APQ8064: Add pinctrl support
  ARM: dts: qcom: Add TLMM DT node for APQ8084
  ARM: dts: qcom: Add initial IFC6540 board device tree
  ARM: dts: msm: Add 8058 PMIC to ssbi bus
  ARM: dts: msm: Add 8921 PMIC to ssbi bus
  ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees
  ARM: dts: qcom: Add APQ8084 serial port DT node
  ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node

Signed-off-by: Olof Johansson <olof@lixom.net>
  • Loading branch information
Olof Johansson committed Sep 24, 2014
2 parents 8adc36b + edb81ca commit 007c7fd
Show file tree
Hide file tree
Showing 14 changed files with 659 additions and 0 deletions.
2 changes: 2 additions & 0 deletions arch/arm/boot/dts/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -346,7 +346,9 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8064-ifc6410.dtb \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
Expand Down
12 changes: 12 additions & 0 deletions arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
Original file line number Diff line number Diff line change
Expand Up @@ -12,5 +12,17 @@
status = "ok";
};
};

amba {
/* eMMC */
sdcc1: sdcc@12400000 {
status = "okay";
};

/* External micro SD card */
sdcc3: sdcc@12180000 {
status = "okay";
};
};
};
};
103 changes: 103 additions & 0 deletions arch/arm/boot/dts/qcom-apq8064.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,9 @@

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
model = "Qualcomm APQ8064";
Expand Down Expand Up @@ -70,6 +72,27 @@
ranges;
compatible = "simple-bus";

tlmm_pinmux: pinctrl@800000 {
compatible = "qcom,apq8064-pinctrl";
reg = <0x800000 0x4000>;

gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

pinctrl-names = "default";
pinctrl-0 = <&ps_hold>;

ps_hold: ps_hold {
mux {
pins = "gpio78";
function = "ps_hold";
};
};
};

intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
Expand Down Expand Up @@ -166,5 +189,85 @@
#clock-cells = <1>;
#reset-cells = <1>;
};

mmcc: clock-controller@4000000 {
compatible = "qcom,mmcc-apq8064";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

/* Temporary fixed regulator */
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-always-on;
};

sdcc1bam:dma@12402000{
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
interrupts = <0 98 0>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};

sdcc3bam:dma@12182000{
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <0 96 0>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};

amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sdcc1: sdcc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
};

sdcc3: sdcc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
no-1-8-v;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
};
};
};
};
23 changes: 23 additions & 0 deletions arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
#include "qcom-apq8084.dtsi"

/ {
model = "Qualcomm APQ8084/IFC6540";
compatible = "qcom,apq8084-ifc6540", "qcom,apq8084";

soc {
serial@f995e000 {
status = "okay";
};

sdhci@f9824900 {
bus-width = <8>;
non-removable;
status = "okay";
};

sdhci@f98a4900 {
cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
};
};
6 changes: 6 additions & 0 deletions arch/arm/boot/dts/qcom-apq8084-mtp.dts
Original file line number Diff line number Diff line change
Expand Up @@ -3,4 +3,10 @@
/ {
model = "Qualcomm APQ 8084-MTP";
compatible = "qcom,apq8084-mtp", "qcom,apq8084";

soc {
serial@f995e000 {
status = "okay";
};
};
};
51 changes: 51 additions & 0 deletions arch/arm/boot/dts/qcom-apq8084.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,9 @@

#include "skeleton.dtsi"

#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>

/ {
model = "Qualcomm APQ 8084";
compatible = "qcom,apq8084";
Expand Down Expand Up @@ -175,5 +178,53 @@
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};

gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-apq8084";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0xfc400000 0x4000>;
};

tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
};

serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
interrupts = <0 114 0x0>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};

sdhci@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};

sdhci@f98a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
};
};
85 changes: 85 additions & 0 deletions arch/arm/boot/dts/qcom-ipq8064-ap148.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,85 @@
#include "qcom-ipq8064-v1.0.dtsi"

/ {
model = "Qualcomm IPQ8064/AP148";
compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";

reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};

soc {
pinmux@800000 {
i2c4_pins: i2c4_pinmux {
pins = "gpio12", "gpio13";
function = "gsbi4";
bias-disable;
};

spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
drive-strength = <10>;
bias-none;
};
};
};

gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "ok";
serial@16340000 {
status = "ok";
};

i2c4: i2c@16380000 {
status = "ok";

clock-frequency = <200000>;

pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
};

gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
status = "ok";

spi4: spi@1a280000 {
status = "ok";
spi-max-frequency = <50000000>;

pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";

cs-gpios = <&qcom_pinmux 20 0>;

flash: m25p80@0 {
compatible = "s25fl256s1";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;

partition@0 {
label = "rootfs";
reg = <0x0 0x1000000>;
};

partition@1 {
label = "scratch";
reg = <0x1000000 0x1000000>;
};
};
};
};
};
};
1 change: 1 addition & 0 deletions arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
#include "qcom-ipq8064.dtsi"
Loading

0 comments on commit 007c7fd

Please sign in to comment.