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clocksource/drivers/arm_arch_timer: Work around broken CVAL implement…
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The Applied Micro XGene-1 SoC has a busted implementation of the
CVAL register: it looks like it is based on TVAL instead of the
other way around. The net effect of this implementation blunder
is that the maximum deadline you can program in the timer is
32bit wide.

Use a MIDR check to notice the broken CPU, and reduce the width
of the timer to 32bit.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-10-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Marc Zyngier authored and Daniel Lezcano committed Oct 17, 2021
1 parent 30aa08d commit 012f188
Showing 1 changed file with 27 additions and 1 deletion.
28 changes: 27 additions & 1 deletion drivers/clocksource/arm_arch_timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -780,9 +780,32 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
return 0;
}

static u64 __arch_timer_check_delta(void)
{
#ifdef CONFIG_ARM64
const struct midr_range broken_cval_midrs[] = {
/*
* XGene-1 implements CVAL in terms of TVAL, meaning
* that the maximum timer range is 32bit. Shame on them.
*/
MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
APM_CPU_PART_POTENZA)),
{},
};

if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {
pr_warn_once("Broken CNTx_CVAL_EL1, limiting width to 32bits");
return CLOCKSOURCE_MASK(32);
}
#endif
return CLOCKSOURCE_MASK(56);
}

static void __arch_timer_setup(unsigned type,
struct clock_event_device *clk)
{
u64 max_delta;

clk->features = CLOCK_EVT_FEAT_ONESHOT;

if (type == ARCH_TIMER_TYPE_CP15) {
Expand Down Expand Up @@ -814,6 +837,7 @@ static void __arch_timer_setup(unsigned type,
}

clk->set_next_event = sne;
max_delta = __arch_timer_check_delta();
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
Expand All @@ -830,11 +854,13 @@ static void __arch_timer_setup(unsigned type,
clk->set_next_event =
arch_timer_set_next_event_phys_mem;
}

max_delta = CLOCKSOURCE_MASK(56);
}

clk->set_state_shutdown(clk);

clockevents_config_and_register(clk, arch_timer_rate, 0xf, CLOCKSOURCE_MASK(56));
clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
}

static void arch_timer_evtstrm_enable(int divider)
Expand Down

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