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xtensa: fix build for configs without cache options
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- make cache-related assembly macros empty if core doesn't have
  corresponding cache type;
- don't initialize cache attributes in instruction/data TLB entries if
  there's no corresponding cache type.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Max Filippov committed Nov 2, 2015
1 parent 5029615 commit 01618bd
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Showing 2 changed files with 35 additions and 4 deletions.
26 changes: 26 additions & 0 deletions arch/xtensa/include/asm/cacheasm.h
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,9 @@

.macro ___unlock_dcache_all ar at

#if XCHAL_DCACHE_SIZE
__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
#endif

.endm

Expand All @@ -90,87 +92,111 @@

.macro ___flush_invalidate_dcache_all ar at

#if XCHAL_DCACHE_SIZE
__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___flush_dcache_all ar at

#if XCHAL_DCACHE_SIZE
__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___invalidate_dcache_all ar at

#if XCHAL_DCACHE_SIZE
__loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___invalidate_icache_all ar at

#if XCHAL_ICACHE_SIZE
__loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
XCHAL_ICACHE_LINEWIDTH
#endif

.endm



.macro ___flush_invalidate_dcache_range ar as at

#if XCHAL_DCACHE_SIZE
__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___flush_dcache_range ar as at

#if XCHAL_DCACHE_SIZE
__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___invalidate_dcache_range ar as at

#if XCHAL_DCACHE_SIZE
__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___invalidate_icache_range ar as at

#if XCHAL_ICACHE_SIZE
__loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
#endif

.endm



.macro ___flush_invalidate_dcache_page ar as

#if XCHAL_DCACHE_SIZE
__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___flush_dcache_page ar as

#if XCHAL_DCACHE_SIZE
__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___invalidate_dcache_page ar as

#if XCHAL_DCACHE_SIZE
__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
#endif

.endm


.macro ___invalidate_icache_page ar as

#if XCHAL_ICACHE_SIZE
__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
#endif

.endm
13 changes: 9 additions & 4 deletions arch/xtensa/include/asm/initialize_mmu.h
Original file line number Diff line number Diff line change
Expand Up @@ -161,7 +161,8 @@
#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
XCHAL_HAVE_SPANNING_WAY */

#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
(XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE)
/* Enable data and instruction cache in the DEFAULT_MEMORY region
* if the processor has DTLB and ITLB.
*/
Expand All @@ -175,14 +176,18 @@
1:
sub a9, a9, a8
2:
#if XCHAL_DCACHE_SIZE
rdtlb1 a3, a5
ritlb1 a4, a5
and a3, a3, a6
and a4, a4, a6
or a3, a3, a7
or a4, a4, a7
wdtlb a3, a5
#endif
#if XCHAL_ICACHE_SIZE
ritlb1 a4, a5
and a4, a4, a6
or a4, a4, a7
witlb a4, a5
#endif
add a5, a5, a8
bltu a8, a9, 1b

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