drm/amd/display: Refactor DCN4x and related code

[why & how] Refactor existing code related to DCN4x for better code sharing with other modules. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Swapnil Patel <Swapnil.Patel@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
mariux64 · Feb 25, 2025 · 02a2793 · 02a2793
1 parent f6d1727
commit 02a2793
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Showing 13 changed files with 282 additions and 249 deletions.
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
@@ -379,53 +379,55 @@ struct dccg_mask {
 	DCCG401_REG_FIELD_LIST(uint32_t)
 };
 
+#define DCCG_REG_VARIABLE_LIST \
+	uint32_t DPPCLK_DTO_CTRL; \
+	uint32_t DPPCLK_DTO_PARAM[6]; \
+	uint32_t REFCLK_CNTL; \
+	uint32_t DISPCLK_FREQ_CHANGE_CNTL; \
+	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \
+	uint32_t HDMICHARCLK_CLOCK_CNTL[6]; \
+	uint32_t PHYASYMCLK_CLOCK_CNTL; \
+	uint32_t PHYBSYMCLK_CLOCK_CNTL; \
+	uint32_t PHYCSYMCLK_CLOCK_CNTL; \
+	uint32_t PHYDSYMCLK_CLOCK_CNTL; \
+	uint32_t PHYESYMCLK_CLOCK_CNTL; \
+	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \
+	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \
+	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; \
+	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; \
+	uint32_t DCCG_AUDIO_DTO_SOURCE; \
+	uint32_t DPSTREAMCLK_CNTL; \
+	uint32_t HDMISTREAMCLK_CNTL; \
+	uint32_t SYMCLK32_SE_CNTL; \
+	uint32_t SYMCLK32_LE_CNTL; \
+	uint32_t DENTIST_DISPCLK_CNTL; \
+	uint32_t DSCCLK_DTO_CTRL; \
+	uint32_t DSCCLK0_DTO_PARAM; \
+	uint32_t DSCCLK1_DTO_PARAM; \
+	uint32_t DSCCLK2_DTO_PARAM; \
+	uint32_t DSCCLK3_DTO_PARAM; \
+	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; \
+	uint32_t DPSTREAMCLK_GATE_DISABLE; \
+	uint32_t DCCG_GATE_DISABLE_CNTL; \
+	uint32_t DCCG_GATE_DISABLE_CNTL2; \
+	uint32_t DCCG_GATE_DISABLE_CNTL3; \
+	uint32_t HDMISTREAMCLK0_DTO_PARAM; \
+	uint32_t DCCG_GATE_DISABLE_CNTL4; \
+	uint32_t OTG_PIXEL_RATE_DIV; \
+	uint32_t DTBCLK_P_CNTL; \
+	uint32_t DPPCLK_CTRL; \
+	uint32_t DCCG_GATE_DISABLE_CNTL5; \
+	uint32_t DCCG_GATE_DISABLE_CNTL6; \
+	uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; \
+	uint32_t SYMCLKA_CLOCK_ENABLE; \
+	uint32_t SYMCLKB_CLOCK_ENABLE; \
+	uint32_t SYMCLKC_CLOCK_ENABLE; \
+	uint32_t SYMCLKD_CLOCK_ENABLE; \
+	uint32_t SYMCLKE_CLOCK_ENABLE; \
+	uint32_t DP_DTO_MODULO[MAX_PIPES]; \
+	uint32_t DP_DTO_PHASE[MAX_PIPES]
 struct dccg_registers {
-	uint32_t DPPCLK_DTO_CTRL;
-	uint32_t DPPCLK_DTO_PARAM[6];
-	uint32_t REFCLK_CNTL;
-	uint32_t DISPCLK_FREQ_CHANGE_CNTL;
-	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
-	uint32_t HDMICHARCLK_CLOCK_CNTL[6];
-	uint32_t PHYASYMCLK_CLOCK_CNTL;
-	uint32_t PHYBSYMCLK_CLOCK_CNTL;
-	uint32_t PHYCSYMCLK_CLOCK_CNTL;
-	uint32_t PHYDSYMCLK_CLOCK_CNTL;
-	uint32_t PHYESYMCLK_CLOCK_CNTL;
-	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
-	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
-	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
-	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;
-	uint32_t DCCG_AUDIO_DTO_SOURCE;
-	uint32_t DPSTREAMCLK_CNTL;
-	uint32_t HDMISTREAMCLK_CNTL;
-	uint32_t SYMCLK32_SE_CNTL;
-	uint32_t SYMCLK32_LE_CNTL;
-	uint32_t DENTIST_DISPCLK_CNTL;
-	uint32_t DSCCLK_DTO_CTRL;
-	uint32_t DSCCLK0_DTO_PARAM;
-	uint32_t DSCCLK1_DTO_PARAM;
-	uint32_t DSCCLK2_DTO_PARAM;
-	uint32_t DSCCLK3_DTO_PARAM;
-	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
-	uint32_t DPSTREAMCLK_GATE_DISABLE;
-	uint32_t DCCG_GATE_DISABLE_CNTL;
-	uint32_t DCCG_GATE_DISABLE_CNTL2;
-	uint32_t DCCG_GATE_DISABLE_CNTL3;
-	uint32_t HDMISTREAMCLK0_DTO_PARAM;
-	uint32_t DCCG_GATE_DISABLE_CNTL4;
-	uint32_t OTG_PIXEL_RATE_DIV;
-	uint32_t DTBCLK_P_CNTL;
-	uint32_t DPPCLK_CTRL;
-	uint32_t DCCG_GATE_DISABLE_CNTL5;
-	uint32_t DCCG_GATE_DISABLE_CNTL6;
-	uint32_t DCCG_GLOBAL_FGCG_REP_CNTL;
-	uint32_t SYMCLKA_CLOCK_ENABLE;
-	uint32_t SYMCLKB_CLOCK_ENABLE;
-	uint32_t SYMCLKC_CLOCK_ENABLE;
-	uint32_t SYMCLKD_CLOCK_ENABLE;
-	uint32_t SYMCLKE_CLOCK_ENABLE;
-	uint32_t DP_DTO_MODULO[MAX_PIPES];
-	uint32_t DP_DTO_PHASE[MAX_PIPES];
+	DCCG_REG_VARIABLE_LIST;
 };
 
 struct dcn_dccg {

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -531,7 +531,7 @@ static void dccg401_enable_dpstreamclk(struct dccg *dccg, int otg_inst, int dp_h
 			DPSTREAMCLK_ROOT_GATE_DISABLE, 1);
 }
 
-static void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)
+void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
@@ -208,6 +208,8 @@ void dccg401_enable_symclk32_le(
 void dccg401_disable_symclk32_le(
 		struct dccg *dccg,
 		int hpo_le_inst);
+void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst);
+void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst);
 void dccg401_set_ref_dscclk(struct dccg *dccg,
 				uint32_t dsc_inst);
 void dccg401_set_src_sel(
@@ -228,14 +230,11 @@ void dccg401_set_dp_dto(
 		const struct dp_dto_params *params);
 void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);
 void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);
-
 void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst);
 void dccg401_set_dtbclk_p_src(
 		struct dccg *dccg,
 		enum streamclk_source src,
 		uint32_t otg_inst);
-
-
 struct dccg *dccg401_create(
 	struct dc_context *ctx,
 	const struct dccg_registers *regs,

diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
@@ -100,7 +100,7 @@ void enc401_stream_encoder_dvi_set_stream_attribute(
 }
 
 /* setup stream encoder in hdmi mode */
-static void enc401_stream_encoder_hdmi_set_stream_attribute(
+void enc401_stream_encoder_hdmi_set_stream_attribute(
 	struct stream_encoder *enc,
 	struct dc_crtc_timing *crtc_timing,
 	int actual_pix_clk_khz,

diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
@@ -232,4 +232,9 @@ void enc401_stream_encoder_map_to_link(
 		uint32_t stream_enc_inst,
 		uint32_t link_enc_inst);
 void enc401_read_state(struct stream_encoder *enc, struct enc_state *s);
+void enc401_stream_encoder_hdmi_set_stream_attribute(
+	struct stream_encoder *enc,
+	struct dc_crtc_timing *crtc_timing,
+	int actual_pix_clk_khz,
+	bool enable_audio);
 #endif /* __DC_DIO_STREAM_ENCODER_DCN401_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -33,7 +33,6 @@
 #include "dml2_dc_resource_mgmt.h"
 #include "dml21_wrapper.h"
 
-
 static void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
 {
 	if (dml2->config.use_native_soc_bb_construction)
@@ -792,7 +791,7 @@ bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options
 	// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete.
 	if ((in_dc->debug.using_dml21)
 			&& (in_dc->ctx->dce_version == DCN_VERSION_4_01
-				))
+		))
 		return dml21_create(in_dc, dml2, config);
 
 	// Allocate Mode Lib Ctx

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
@@ -567,80 +567,82 @@
 	type ISHARP_NLDELTA_SCLIP_PIVOT_N;	\
 	type ISHARP_NLDELTA_SCLIP_SLOPE_N
 
+#define DPP_REG_VARIABLE_LIST_DCN401 \
+	DPP_DCN3_REG_VARIABLE_LIST_COMMON; \
+	uint32_t CURSOR0_FP_SCALE_BIAS_G_Y; \
+	uint32_t CURSOR0_FP_SCALE_BIAS_RB_CRCB; \
+	uint32_t CUR0_MATRIX_MODE; \
+	uint32_t CUR0_MATRIX_C11_C12_A; \
+	uint32_t CUR0_MATRIX_C13_C14_A; \
+	uint32_t CUR0_MATRIX_C21_C22_A; \
+	uint32_t CUR0_MATRIX_C23_C24_A; \
+	uint32_t CUR0_MATRIX_C31_C32_A; \
+	uint32_t CUR0_MATRIX_C33_C34_A; \
+	uint32_t CUR0_MATRIX_C11_C12_B; \
+	uint32_t CUR0_MATRIX_C13_C14_B; \
+	uint32_t CUR0_MATRIX_C21_C22_B; \
+	uint32_t CUR0_MATRIX_C23_C24_B; \
+	uint32_t CUR0_MATRIX_C31_C32_B; \
+	uint32_t CUR0_MATRIX_C33_C34_B; \
+	uint32_t DSCL_SC_MODE; \
+	uint32_t DSCL_EASF_H_MODE; \
+	uint32_t DSCL_EASF_H_BF_CNTL; \
+	uint32_t DSCL_EASF_H_RINGEST_EVENTAP_REDUCE; \
+	uint32_t DSCL_EASF_H_RINGEST_EVENTAP_GAIN; \
+	uint32_t DSCL_EASF_H_BF_FINAL_MAX_MIN; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG0; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG1; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG2; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG3; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG4; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG5; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG6; \
+	uint32_t DSCL_EASF_H_BF1_PWL_SEG7; \
+	uint32_t DSCL_EASF_H_BF3_PWL_SEG0; \
+	uint32_t DSCL_EASF_H_BF3_PWL_SEG1; \
+	uint32_t DSCL_EASF_H_BF3_PWL_SEG2; \
+	uint32_t DSCL_EASF_H_BF3_PWL_SEG3; \
+	uint32_t DSCL_EASF_H_BF3_PWL_SEG4; \
+	uint32_t DSCL_EASF_H_BF3_PWL_SEG5; \
+	uint32_t DSCL_EASF_V_MODE; \
+	uint32_t DSCL_EASF_V_BF_CNTL; \
+	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL1; \
+	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL2; \
+	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL3; \
+	uint32_t DSCL_EASF_V_RINGEST_EVENTAP_REDUCE; \
+	uint32_t DSCL_EASF_V_RINGEST_EVENTAP_GAIN; \
+	uint32_t DSCL_EASF_V_BF_FINAL_MAX_MIN; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG0; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG1; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG2; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG3; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG4; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG5; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG6; \
+	uint32_t DSCL_EASF_V_BF1_PWL_SEG7; \
+	uint32_t DSCL_EASF_V_BF3_PWL_SEG0; \
+	uint32_t DSCL_EASF_V_BF3_PWL_SEG1; \
+	uint32_t DSCL_EASF_V_BF3_PWL_SEG2; \
+	uint32_t DSCL_EASF_V_BF3_PWL_SEG3; \
+	uint32_t DSCL_EASF_V_BF3_PWL_SEG4; \
+	uint32_t DSCL_EASF_V_BF3_PWL_SEG5; \
+	uint32_t DSCL_SC_MATRIX_C0C1; \
+	uint32_t DSCL_SC_MATRIX_C2C3; \
+	uint32_t ISHARP_MODE; \
+	uint32_t ISHARP_NOISEDET_THRESHOLD; \
+	uint32_t ISHARP_NOISE_GAIN_PWL; \
+	uint32_t ISHARP_LBA_PWL_SEG0; \
+	uint32_t ISHARP_LBA_PWL_SEG1; \
+	uint32_t ISHARP_LBA_PWL_SEG2; \
+	uint32_t ISHARP_LBA_PWL_SEG3; \
+	uint32_t ISHARP_LBA_PWL_SEG4; \
+	uint32_t ISHARP_LBA_PWL_SEG5; \
+	uint32_t ISHARP_DELTA_CTRL; \
+	uint32_t ISHARP_DELTA_DATA; \
+	uint32_t ISHARP_DELTA_INDEX; \
+	uint32_t ISHARP_NLDELTA_SOFT_CLIP
 struct dcn401_dpp_registers {
-	DPP_DCN3_REG_VARIABLE_LIST_COMMON;
-	uint32_t CURSOR0_FP_SCALE_BIAS_G_Y;
-	uint32_t CURSOR0_FP_SCALE_BIAS_RB_CRCB;
-	uint32_t CUR0_MATRIX_MODE;
-	uint32_t CUR0_MATRIX_C11_C12_A;
-	uint32_t CUR0_MATRIX_C13_C14_A;
-	uint32_t CUR0_MATRIX_C21_C22_A;
-	uint32_t CUR0_MATRIX_C23_C24_A;
-	uint32_t CUR0_MATRIX_C31_C32_A;
-	uint32_t CUR0_MATRIX_C33_C34_A;
-	uint32_t CUR0_MATRIX_C11_C12_B;
-	uint32_t CUR0_MATRIX_C13_C14_B;
-	uint32_t CUR0_MATRIX_C21_C22_B;
-	uint32_t CUR0_MATRIX_C23_C24_B;
-	uint32_t CUR0_MATRIX_C31_C32_B;
-	uint32_t CUR0_MATRIX_C33_C34_B;
-	uint32_t DSCL_SC_MODE;
-	uint32_t DSCL_EASF_H_MODE;
-	uint32_t DSCL_EASF_H_BF_CNTL;
-	uint32_t DSCL_EASF_H_RINGEST_EVENTAP_REDUCE;
-	uint32_t DSCL_EASF_H_RINGEST_EVENTAP_GAIN;
-	uint32_t DSCL_EASF_H_BF_FINAL_MAX_MIN;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG0;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG1;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG2;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG3;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG4;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG5;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG6;
-	uint32_t DSCL_EASF_H_BF1_PWL_SEG7;
-	uint32_t DSCL_EASF_H_BF3_PWL_SEG0;
-	uint32_t DSCL_EASF_H_BF3_PWL_SEG1;
-	uint32_t DSCL_EASF_H_BF3_PWL_SEG2;
-	uint32_t DSCL_EASF_H_BF3_PWL_SEG3;
-	uint32_t DSCL_EASF_H_BF3_PWL_SEG4;
-	uint32_t DSCL_EASF_H_BF3_PWL_SEG5;
-	uint32_t DSCL_EASF_V_MODE;
-	uint32_t DSCL_EASF_V_BF_CNTL;
-	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL1;
-	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL2;
-	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL3;
-	uint32_t DSCL_EASF_V_RINGEST_EVENTAP_REDUCE;
-	uint32_t DSCL_EASF_V_RINGEST_EVENTAP_GAIN;
-	uint32_t DSCL_EASF_V_BF_FINAL_MAX_MIN;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG0;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG1;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG2;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG3;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG4;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG5;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG6;
-	uint32_t DSCL_EASF_V_BF1_PWL_SEG7;
-	uint32_t DSCL_EASF_V_BF3_PWL_SEG0;
-	uint32_t DSCL_EASF_V_BF3_PWL_SEG1;
-	uint32_t DSCL_EASF_V_BF3_PWL_SEG2;
-	uint32_t DSCL_EASF_V_BF3_PWL_SEG3;
-	uint32_t DSCL_EASF_V_BF3_PWL_SEG4;
-	uint32_t DSCL_EASF_V_BF3_PWL_SEG5;
-	uint32_t DSCL_SC_MATRIX_C0C1;
-	uint32_t DSCL_SC_MATRIX_C2C3;
-	uint32_t ISHARP_MODE;
-	uint32_t ISHARP_NOISEDET_THRESHOLD;
-	uint32_t ISHARP_NOISE_GAIN_PWL;
-	uint32_t ISHARP_LBA_PWL_SEG0;
-	uint32_t ISHARP_LBA_PWL_SEG1;
-	uint32_t ISHARP_LBA_PWL_SEG2;
-	uint32_t ISHARP_LBA_PWL_SEG3;
-	uint32_t ISHARP_LBA_PWL_SEG4;
-	uint32_t ISHARP_LBA_PWL_SEG5;
-	uint32_t ISHARP_DELTA_CTRL;
-	uint32_t ISHARP_DELTA_DATA;
-	uint32_t ISHARP_DELTA_INDEX;
-	uint32_t ISHARP_NLDELTA_SOFT_CLIP;
+	DPP_REG_VARIABLE_LIST_DCN401;
 };
 
 struct dcn401_dpp_shift {

diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
@@ -262,7 +262,7 @@ void dcn31_hpo_dp_link_enc_set_link_test_pattern(
 	}
 }
 
-static void fill_stream_allocation_row_info(
+void dcn31_fill_stream_allocation_row_info(
 		const struct link_mst_stream_allocation *stream_allocation,
 		uint32_t *src,
 		uint32_t *slots)
@@ -296,7 +296,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
 	/* we should clean-up table each time */
 
 	if (table->stream_count >= 1) {
-		fill_stream_allocation_row_info(
+		dcn31_fill_stream_allocation_row_info(
 			&table->stream_allocations[0],
 			&src,
 			&slots);
@@ -310,7 +310,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
 			SAT_SLOT_COUNT, slots);
 
 	if (table->stream_count >= 2) {
-		fill_stream_allocation_row_info(
+		dcn31_fill_stream_allocation_row_info(
 			&table->stream_allocations[1],
 			&src,
 			&slots);
@@ -324,7 +324,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
 			SAT_SLOT_COUNT, slots);
 
 	if (table->stream_count >= 3) {
-		fill_stream_allocation_row_info(
+		dcn31_fill_stream_allocation_row_info(
 			&table->stream_allocations[2],
 			&src,
 			&slots);
@@ -338,7 +338,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
 			SAT_SLOT_COUNT, slots);
 
 	if (table->stream_count >= 4) {
-		fill_stream_allocation_row_info(
+		dcn31_fill_stream_allocation_row_info(
 			&table->stream_allocations[3],
 			&src,
 			&slots);

diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h
@@ -226,4 +226,10 @@ void dcn31_hpo_dp_link_enc_set_ffe(
 	const struct dc_link_settings *link_settings,
 	uint8_t ffe_preset);
 
+
+void dcn31_fill_stream_allocation_row_info(
+		const struct link_mst_stream_allocation *stream_allocation,
+		uint32_t *src,
+		uint32_t *slots);
+
 #endif   // __DAL_DCN31_HPO_LINK_ENCODER_H__
diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h
@@ -62,4 +62,7 @@ void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31,
 	const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
 	const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask);
 
+bool dcn32_hpo_dp_link_enc_is_in_alt_mode(
+		struct hpo_dp_link_encoder *enc);
+
 #endif   // __DAL_DCN32_HPO_DP_LINK_ENCODER_H__
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
@@ -1244,6 +1244,7 @@ struct dce_hwseq_registers {
 	type DOMAIN24_PGFSM_PWR_STATUS; \
 	type DOMAIN25_PGFSM_PWR_STATUS; \
 	type DOMAIN_DESIRED_PWR_STATE;
+
 struct dce_hwseq_shift {
 	HWSEQ_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)