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clockevents/driversi/mps2: add MPS2 Timer driver
MPS2 platform has simple 32 bits general purpose countdown timers. The driver uses the first detected timer as a clocksource and the rest of the timers as a clockevent Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Vladimir Murzin
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Daniel Lezcano
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Apr 28, 2016
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/* | ||
* Copyright (C) 2015 ARM Limited | ||
* | ||
* Author: Vladimir Murzin <vladimir.murzin@arm.com> | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
* | ||
*/ | ||
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
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#include <linux/clk.h> | ||
#include <linux/clockchips.h> | ||
#include <linux/clocksource.h> | ||
#include <linux/err.h> | ||
#include <linux/interrupt.h> | ||
#include <linux/io.h> | ||
#include <linux/irq.h> | ||
#include <linux/of_address.h> | ||
#include <linux/of.h> | ||
#include <linux/of_irq.h> | ||
#include <linux/sched_clock.h> | ||
#include <linux/slab.h> | ||
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#define TIMER_CTRL 0x0 | ||
#define TIMER_CTRL_ENABLE BIT(0) | ||
#define TIMER_CTRL_IE BIT(3) | ||
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#define TIMER_VALUE 0x4 | ||
#define TIMER_RELOAD 0x8 | ||
#define TIMER_INT 0xc | ||
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struct clockevent_mps2 { | ||
void __iomem *reg; | ||
u32 clock_count_per_tick; | ||
struct clock_event_device clkevt; | ||
}; | ||
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static void __iomem *sched_clock_base; | ||
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static u64 notrace mps2_sched_read(void) | ||
{ | ||
return ~readl_relaxed(sched_clock_base + TIMER_VALUE); | ||
} | ||
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static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c) | ||
{ | ||
return container_of(c, struct clockevent_mps2, clkevt); | ||
} | ||
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static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset) | ||
{ | ||
writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); | ||
} | ||
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static int mps2_timer_shutdown(struct clock_event_device *ce) | ||
{ | ||
clockevent_mps2_writel(0, ce, TIMER_RELOAD); | ||
clockevent_mps2_writel(0, ce, TIMER_CTRL); | ||
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return 0; | ||
} | ||
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static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce) | ||
{ | ||
clockevent_mps2_writel(next, ce, TIMER_VALUE); | ||
clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); | ||
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return 0; | ||
} | ||
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static int mps2_timer_set_periodic(struct clock_event_device *ce) | ||
{ | ||
u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; | ||
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clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD); | ||
clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE); | ||
clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); | ||
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return 0; | ||
} | ||
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static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id) | ||
{ | ||
struct clockevent_mps2 *ce = dev_id; | ||
u32 status = readl_relaxed(ce->reg + TIMER_INT); | ||
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if (!status) { | ||
pr_warn("spurious interrupt\n"); | ||
return IRQ_NONE; | ||
} | ||
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writel_relaxed(1, ce->reg + TIMER_INT); | ||
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ce->clkevt.event_handler(&ce->clkevt); | ||
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return IRQ_HANDLED; | ||
} | ||
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static int __init mps2_clockevent_init(struct device_node *np) | ||
{ | ||
void __iomem *base; | ||
struct clk *clk = NULL; | ||
struct clockevent_mps2 *ce; | ||
u32 rate; | ||
int irq, ret; | ||
const char *name = "mps2-clkevt"; | ||
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ret = of_property_read_u32(np, "clock-frequency", &rate); | ||
if (ret) { | ||
clk = of_clk_get(np, 0); | ||
if (IS_ERR(clk)) { | ||
ret = PTR_ERR(clk); | ||
pr_err("failed to get clock for clockevent: %d\n", ret); | ||
goto out; | ||
} | ||
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ret = clk_prepare_enable(clk); | ||
if (ret) { | ||
pr_err("failed to enable clock for clockevent: %d\n", ret); | ||
goto out_clk_put; | ||
} | ||
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rate = clk_get_rate(clk); | ||
} | ||
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base = of_iomap(np, 0); | ||
if (!base) { | ||
ret = -EADDRNOTAVAIL; | ||
pr_err("failed to map register for clockevent: %d\n", ret); | ||
goto out_clk_disable; | ||
} | ||
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irq = irq_of_parse_and_map(np, 0); | ||
if (!irq) { | ||
ret = -ENOENT; | ||
pr_err("failed to get irq for clockevent: %d\n", ret); | ||
goto out_iounmap; | ||
} | ||
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ce = kzalloc(sizeof(*ce), GFP_KERNEL); | ||
if (!ce) { | ||
ret = -ENOMEM; | ||
goto out_iounmap; | ||
} | ||
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ce->reg = base; | ||
ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ); | ||
ce->clkevt.irq = irq; | ||
ce->clkevt.name = name; | ||
ce->clkevt.rating = 200; | ||
ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; | ||
ce->clkevt.cpumask = cpu_possible_mask; | ||
ce->clkevt.set_state_shutdown = mps2_timer_shutdown, | ||
ce->clkevt.set_state_periodic = mps2_timer_set_periodic, | ||
ce->clkevt.set_state_oneshot = mps2_timer_shutdown, | ||
ce->clkevt.set_next_event = mps2_timer_set_next_event; | ||
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/* Ensure timer is disabled */ | ||
writel_relaxed(0, base + TIMER_CTRL); | ||
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ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce); | ||
if (ret) { | ||
pr_err("failed to request irq for clockevent: %d\n", ret); | ||
goto out_kfree; | ||
} | ||
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clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff); | ||
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return 0; | ||
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out_kfree: | ||
kfree(ce); | ||
out_iounmap: | ||
iounmap(base); | ||
out_clk_disable: | ||
/* clk_{disable, unprepare, put}() can handle NULL as a parameter */ | ||
clk_disable_unprepare(clk); | ||
out_clk_put: | ||
clk_put(clk); | ||
out: | ||
return ret; | ||
} | ||
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static int __init mps2_clocksource_init(struct device_node *np) | ||
{ | ||
void __iomem *base; | ||
struct clk *clk = NULL; | ||
u32 rate; | ||
int ret; | ||
const char *name = "mps2-clksrc"; | ||
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ret = of_property_read_u32(np, "clock-frequency", &rate); | ||
if (ret) { | ||
clk = of_clk_get(np, 0); | ||
if (IS_ERR(clk)) { | ||
ret = PTR_ERR(clk); | ||
pr_err("failed to get clock for clocksource: %d\n", ret); | ||
goto out; | ||
} | ||
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ret = clk_prepare_enable(clk); | ||
if (ret) { | ||
pr_err("failed to enable clock for clocksource: %d\n", ret); | ||
goto out_clk_put; | ||
} | ||
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rate = clk_get_rate(clk); | ||
} | ||
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base = of_iomap(np, 0); | ||
if (!base) { | ||
ret = -EADDRNOTAVAIL; | ||
pr_err("failed to map register for clocksource: %d\n", ret); | ||
goto out_clk_disable; | ||
} | ||
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/* Ensure timer is disabled */ | ||
writel_relaxed(0, base + TIMER_CTRL); | ||
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/* ... and set it up as free-running clocksource */ | ||
writel_relaxed(0xffffffff, base + TIMER_VALUE); | ||
writel_relaxed(0xffffffff, base + TIMER_RELOAD); | ||
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writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL); | ||
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ret = clocksource_mmio_init(base + TIMER_VALUE, name, | ||
rate, 200, 32, | ||
clocksource_mmio_readl_down); | ||
if (ret) { | ||
pr_err("failed to init clocksource: %d\n", ret); | ||
goto out_iounmap; | ||
} | ||
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sched_clock_base = base; | ||
sched_clock_register(mps2_sched_read, 32, rate); | ||
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return 0; | ||
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out_iounmap: | ||
iounmap(base); | ||
out_clk_disable: | ||
/* clk_{disable, unprepare, put}() can handle NULL as a parameter */ | ||
clk_disable_unprepare(clk); | ||
out_clk_put: | ||
clk_put(clk); | ||
out: | ||
return ret; | ||
} | ||
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static void __init mps2_timer_init(struct device_node *np) | ||
{ | ||
static int has_clocksource, has_clockevent; | ||
int ret; | ||
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if (!has_clocksource) { | ||
ret = mps2_clocksource_init(np); | ||
if (!ret) { | ||
has_clocksource = 1; | ||
return; | ||
} | ||
} | ||
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if (!has_clockevent) { | ||
ret = mps2_clockevent_init(np); | ||
if (!ret) { | ||
has_clockevent = 1; | ||
return; | ||
} | ||
} | ||
} | ||
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CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init); |