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drm/i915/gvt: cleanup opregion memory allocation code
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According to the spec, ACPI OpRegion must be placed at a physical address
below 4G. That is, for a vGPU it must be associated with a GPA below 4G,
but on host side, it doesn't matter where the backing pages actually are.
So when allocating pages from host, the GFP_DMA32 flag is unnecessary.

Also the allocation is from a sleepable context, so GFP_ATOMIC is also
unnecessary.

This patch also removes INTEL_GVT_OPREGION_PORDER and use get_order()
instead.

Signed-off-by: Jike Song <jike.song@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Jike Song authored and Zhenyu Wang committed Jan 9, 2017
1 parent 4e53789 commit 03551e9
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Showing 2 changed files with 5 additions and 6 deletions.
8 changes: 4 additions & 4 deletions drivers/gpu/drm/i915/gvt/opregion.c
Original file line number Diff line number Diff line change
Expand Up @@ -36,9 +36,9 @@ static int init_vgpu_opregion(struct intel_vgpu *vgpu, u32 gpa)
vgpu->id))
return -EINVAL;

vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_ATOMIC |
GFP_DMA32 | __GFP_ZERO,
INTEL_GVT_OPREGION_PORDER);
vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL |
__GFP_ZERO,
get_order(INTEL_GVT_OPREGION_SIZE));

if (!vgpu_opregion(vgpu)->va)
return -ENOMEM;
Expand Down Expand Up @@ -97,7 +97,7 @@ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu)
if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) {
map_vgpu_opregion(vgpu, false);
free_pages((unsigned long)vgpu_opregion(vgpu)->va,
INTEL_GVT_OPREGION_PORDER);
get_order(INTEL_GVT_OPREGION_SIZE));

vgpu_opregion(vgpu)->va = NULL;
}
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3 changes: 1 addition & 2 deletions drivers/gpu/drm/i915/gvt/reg.h
Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,7 @@
#define INTEL_GVT_OPREGION_PARM 0x204

#define INTEL_GVT_OPREGION_PAGES 2
#define INTEL_GVT_OPREGION_PORDER 1
#define INTEL_GVT_OPREGION_SIZE (2 * 4096)
#define INTEL_GVT_OPREGION_SIZE (INTEL_GVT_OPREGION_PAGES * PAGE_SIZE)

#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)

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