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RDMA/mlx5: Move init and cleanup of UMR to umr.c
The first patch in a series to split UMR logic to a dedicated file. As a start, move the init and cleanup of UMR resources to umr.c. Link: https://lore.kernel.org/r/849e632dd1945a2534712a320cc5779f2149ba96.1649747695.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Michael Guralnik <michaelgur@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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Aharon Landau
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Jason Gunthorpe
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Apr 25, 2022
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,106 @@ | ||
| // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB | ||
| /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */ | ||
|
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| #include "mlx5_ib.h" | ||
| #include "umr.h" | ||
|
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||
| enum { | ||
| MAX_UMR_WR = 128, | ||
| }; | ||
|
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| static int mlx5r_umr_qp_rst2rts(struct mlx5_ib_dev *dev, struct ib_qp *qp) | ||
| { | ||
| struct ib_qp_attr attr = {}; | ||
| int ret; | ||
|
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| attr.qp_state = IB_QPS_INIT; | ||
| attr.port_num = 1; | ||
| ret = ib_modify_qp(qp, &attr, | ||
| IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT); | ||
| if (ret) { | ||
| mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); | ||
| return ret; | ||
| } | ||
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| memset(&attr, 0, sizeof(attr)); | ||
| attr.qp_state = IB_QPS_RTR; | ||
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| ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | ||
| if (ret) { | ||
| mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); | ||
| return ret; | ||
| } | ||
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| memset(&attr, 0, sizeof(attr)); | ||
| attr.qp_state = IB_QPS_RTS; | ||
| ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | ||
| if (ret) { | ||
| mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); | ||
| return ret; | ||
| } | ||
|
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| return 0; | ||
| } | ||
|
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| int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev) | ||
| { | ||
| struct ib_qp_init_attr init_attr = {}; | ||
| struct ib_pd *pd; | ||
| struct ib_cq *cq; | ||
| struct ib_qp *qp; | ||
| int ret; | ||
|
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| pd = ib_alloc_pd(&dev->ib_dev, 0); | ||
| if (IS_ERR(pd)) { | ||
| mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); | ||
| return PTR_ERR(pd); | ||
| } | ||
|
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| cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); | ||
| if (IS_ERR(cq)) { | ||
| mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); | ||
| ret = PTR_ERR(cq); | ||
| goto destroy_pd; | ||
| } | ||
|
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| init_attr.send_cq = cq; | ||
| init_attr.recv_cq = cq; | ||
| init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; | ||
| init_attr.cap.max_send_wr = MAX_UMR_WR; | ||
| init_attr.cap.max_send_sge = 1; | ||
| init_attr.qp_type = MLX5_IB_QPT_REG_UMR; | ||
| init_attr.port_num = 1; | ||
| qp = ib_create_qp(pd, &init_attr); | ||
| if (IS_ERR(qp)) { | ||
| mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); | ||
| ret = PTR_ERR(qp); | ||
| goto destroy_cq; | ||
| } | ||
|
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| ret = mlx5r_umr_qp_rst2rts(dev, qp); | ||
| if (ret) | ||
| goto destroy_qp; | ||
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| dev->umrc.qp = qp; | ||
| dev->umrc.cq = cq; | ||
| dev->umrc.pd = pd; | ||
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| sema_init(&dev->umrc.sem, MAX_UMR_WR); | ||
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| return 0; | ||
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| destroy_qp: | ||
| ib_destroy_qp(qp); | ||
| destroy_cq: | ||
| ib_free_cq(cq); | ||
| destroy_pd: | ||
| ib_dealloc_pd(pd); | ||
| return ret; | ||
| } | ||
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| void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev) | ||
| { | ||
| ib_destroy_qp(dev->umrc.qp); | ||
| ib_free_cq(dev->umrc.cq); | ||
| ib_dealloc_pd(dev->umrc.pd); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,12 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ | ||
| /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */ | ||
|
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| #ifndef _MLX5_IB_UMR_H | ||
| #define _MLX5_IB_UMR_H | ||
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| #include "mlx5_ib.h" | ||
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| int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev); | ||
| void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev); | ||
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| #endif /* _MLX5_IB_UMR_H */ |