Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel…

…/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (24 commits)
  [Blackfin] arch: import defines for BF547 -- it is just like the BF548, but no CAN
  [Blackfin] arch: fix build fails only include header files when enabled
  [Blackfin] arch: declare default INSTALL_PATH for Blackfin ports
  [Blackfin] arch: Encourage users to use the spidev character driver: Provide platform support
  [Blackfin] arch: Enable UART2 and UART3 for bf548
  [Blackfin] arch: Enable NET2272 on BF561-EZkit - remove request_mem_region
  [Blackfin] arch:Fix BUG [#3876] pfbutton test for BTN3 on bf533 don't show complete info
  [Blackfin] arch: remove duplicated definitions of the line discipline numbers N_* in asm-blackfin/termios.h
  [Blackfin] arch: fix building with mtd uclinux by putting the mtd_phys option into the function it actually gets used in
  [Blackfin] arch: simpler header and update dates
  [Blackfin] arch: move the init sections to the end of memory
  [Blackfin] arch: change the trace buffer control start/stop logic in the exception handlers
  [Blackfin] arch: fix typo in printk message
  [Blackfin] arch: this is an ezkit, not a stamp, so fixup the init function name
  [Blackfin] arch: add slightly better help text for CPLB_INFO
  [Blackfin] arch: Fix BUG - Enable ISP1362 driver to work ok with BF561
  [Blackfin] arch: Fix header file information
  [Blackfin] arch: Add Support for ISP1362
  [Blackfin] arch: add support for cmdline partitioning to the BF533-STAMP flash map driver and enable it as a module by default
  [Blackfin] arch: hook up set_irq_wake in Blackfin's irq code
  ...

arch/blackfin/Kconfig

@@ -544,7 +544,7 @@ config EXCPT_IRQ_SYSC_L1
 	default y
 	help
 	  If enabled, the entire ASM lowlevel exception and interrupt entry code
-	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 
+	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 	  (less latency)
 
 config DO_IRQ_L1
@@ -904,29 +904,38 @@ config ARCH_SUSPEND_POSSIBLE
 	depends on !SMP
 
 choice
-	prompt "Select PM Wakeup Event Source"
-	default PM_WAKEUP_GPIO_BY_SIC_IWR
+	prompt "Default Power Saving Mode"
 	depends on PM
-	help
-	  If you have a GPIO already configured as input with the corresponding PORTx_MASK
-	  bit set - "Specify Wakeup Event by SIC_IWR value"
+	default PM_BFIN_SLEEP_DEEPER
+config  PM_BFIN_SLEEP_DEEPER
+	bool "Sleep Deeper"
+	help
+	  Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
+	  power dissipation by disabling the clock to the processor core (CCLK).
+	  Furthermore, Standby sets the internal power supply voltage (VDDINT)
+	  to 0.85 V to provide the greatest power savings, while preserving the
+	  processor state.
+	  The PLL and system clock (SCLK) continue to operate at a very low
+	  frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
+	  the SDRAM is put into Self Refresh Mode. Typically an external event
+	  such as GPIO interrupt or RTC activity wakes up the processor.
+	  Various Peripherals such as UART, SPORT, PPI may not function as
+	  normal during Sleep Deeper, due to the reduced SCLK frequency.
+	  When in the sleep mode, system DMA access to L1 memory is not supported.
+
+config  PM_BFIN_SLEEP
+	bool "Sleep"
+	help
+	  Sleep Mode (High Power Savings) - The sleep mode reduces power
+	  dissipation by disabling the clock to the processor core (CCLK).
+	  The PLL and system clock (SCLK), however, continue to operate in
+	  this mode. Typically an external event or RTC activity will wake
+	  up the processor. When in the sleep mode,
+	  system DMA access to L1 memory is not supported.
+endchoice
 
-config PM_WAKEUP_GPIO_BY_SIC_IWR
-	bool "Specify Wakeup Event by SIC_IWR value"
 config PM_WAKEUP_BY_GPIO
 	bool "Cause Wakeup Event by GPIO"
-config PM_WAKEUP_GPIO_API
-	bool "Configure Wakeup Event by PM GPIO API"
-
-endchoice
-
-config PM_WAKEUP_SIC_IWR
-	hex "Wakeup Events (SIC_IWR)"
-	depends on PM_WAKEUP_GPIO_BY_SIC_IWR
-	default 0x8 if (BF537 || BF536 || BF534)
-	default 0x80 if (BF533 || BF532 || BF531)
-	default 0x80 if (BF54x)
-	default 0x80 if (BF52x)
 
 config PM_WAKEUP_GPIO_NUMBER
 	int "Wakeup GPIO number"

arch/blackfin/Kconfig.debug

@@ -164,7 +164,7 @@ config DUAL_CORE_TEST_MODULE
 config CPLB_INFO
 	bool "Display the CPLB information"
 	help
-	  Display the CPLB information.
+	  Display the CPLB information via /proc/cplbinfo.
 
 config ACCESS_CHECK
 	bool "Check the user pointer address"

arch/blackfin/Makefile

@@ -119,6 +119,7 @@ archclean:
 	$(Q)$(MAKE) $(clean)=$(boot)
 
 
+INSTALL_PATH ?= /tftpboot
 boot := arch/$(ARCH)/boot
 BOOT_TARGETS = vmImage
 PHONY += $(BOOT_TARGETS) install

arch/blackfin/configs/BF533-STAMP_defconfig

@@ -216,8 +216,6 @@ CONFIG_MEM_SIZE=128
 CONFIG_MEM_ADD_WIDTH=11
 CONFIG_ENET_FLASH_PIN=0
 CONFIG_BOOT_LOAD=0x1000
-
-
 CONFIG_BFIN_SCRATCH_REG_RETN=y
 # CONFIG_BFIN_SCRATCH_REG_RETE is not set
 # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -483,7 +481,7 @@ CONFIG_MTD=y
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 
 #
 # User Modules And Translation Layers
@@ -500,8 +498,8 @@ CONFIG_MTD_BLOCK=y
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
 CONFIG_MTD_GEN_PROBE=m
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
@@ -515,8 +513,9 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
 # CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_AMDSTD=m
 # CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=m
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
@@ -526,6 +525,11 @@ CONFIG_MTD_ROM=m
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_BF5xx=m
+CONFIG_BFIN_FLASH_BANK_0=0x7BB0
+CONFIG_BFIN_FLASH_BANK_1=0x7BB0
+CONFIG_BFIN_FLASH_BANK_2=0x7BB0
+CONFIG_BFIN_FLASH_BANK_3=0x7BB0
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 

arch/blackfin/kernel/bfin_dma_5xx.c

@@ -104,6 +104,16 @@ int request_dma(unsigned int channel, char *device_id)
 
 	mutex_unlock(&(dma_ch[channel].dmalock));
 
+#ifdef CONFIG_BF54x
+	if (channel >= CH_UART2_RX && channel <= CH_UART3_TX &&
+		strncmp(device_id, "BFIN_UART", 9) == 0)
+		dma_ch[channel].regs->peripheral_map |=
+			(channel - CH_UART2_RX + 0xC);
+	else
+		dma_ch[channel].regs->peripheral_map |=
+			(channel - CH_UART2_RX + 0x6);
+#endif
+
 	dma_ch[channel].device_id = device_id;
 	dma_ch[channel].irq_callback = NULL;
 

arch/blackfin/kernel/bfin_gpio.c

@@ -186,7 +186,7 @@ static struct str_ident {
 	char name[RESOURCE_LABEL_SIZE];
 } str_ident[MAX_RESOURCES];
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM) && !defined(CONFIG_BF54x)
 static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
 static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
 static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -696,9 +696,8 @@ static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
 	return 0;
 }
 
-u32 gpio_pm_setup(void)
+u32 bfin_pm_setup(void)
 {
-	u32 sic_iwr = 0;
 	u16 bank, mask, i, gpio;
 
 	for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
@@ -723,7 +722,8 @@ u32 gpio_pm_setup(void)
 			gpio = i;
 
 			while (mask) {
-				if (mask & 1) {
+				if ((mask & 1) && (wakeup_flags_map[gpio] !=
+					PM_WAKE_IGNORE)) {
 					reserved_gpio_map[gpio_bank(gpio)] |=
 							gpio_bit(gpio);
 					bfin_gpio_wakeup_type(gpio,
@@ -734,21 +734,17 @@ u32 gpio_pm_setup(void)
 				mask >>= 1;
 			}
 
-			sic_iwr |= 1 <<
-				(sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
+			bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
 			gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
 		}
 	}
 
 	AWA_DUMMY_READ(maskb_set);
 
-	if (sic_iwr)
-		return sic_iwr;
-	else
-		return IWR_ENABLE_ALL;
+	return 0;
 }
 
-void gpio_pm_restore(void)
+void bfin_pm_restore(void)
 {
 	u16 bank, mask, i;
 
@@ -768,7 +764,7 @@ void gpio_pm_restore(void)
 
 			reserved_gpio_map[bank] =
 					gpio_bank_saved[bank].reserved;
-
+			bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
 		}
 
 		gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;

arch/blackfin/kernel/cplb-mpu/cplbinit.c

@@ -26,6 +26,10 @@
 #include <asm/cplb.h>
 #include <asm/cplbinit.h>
 
+#if ANOMALY_05000263
+# error the MPU will not function safely while Anomaly 05000263 applies
+#endif
+
 struct cplb_entry icplb_tbl[MAX_CPLBS];
 struct cplb_entry dcplb_tbl[MAX_CPLBS];
 

arch/blackfin/kernel/init_task.c

@@ -57,5 +57,5 @@ EXPORT_SYMBOL(init_task);
  * "init_task" linker map entry.
  */
 union thread_union init_thread_union
-    __attribute__ ((__section__(".data.init_task"))) = {
+    __attribute__ ((__section__(".init_task.data"))) = {
 INIT_THREAD_INFO(init_task)};