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…/benh/powerpc * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (49 commits) powerpc: Fix build bug with binutils < 2.18 and GCC < 4.2 powerpc/eeh: Don't panic when EEH_MAX_FAILS is exceeded fbdev: Teaches offb about palette on radeon r5xx/r6xx powerpc/cell/edac: Log a syndrome code in case of correctable error powerpc/cell: Add DMA_ATTR_WEAK_ORDERING dma attribute and use in Cell IOMMU code powerpc: Indicate which oprofile counters to use while in compat mode powerpc/boot: Change spaces to tabs powerpc: Remove duplicate 6xx option in Kconfig powerpc: Use PPC_LONG and PPC_LONG_ALIGN in lib/string.S powerpc: Use PPC_LONG_ALIGN in uaccess.h powerpc: Add a #define for aligning to a long-sized boundary powerpc: Fix OF parsing of 64 bits PCI addresses powerpc: Use WARN_ON(1) instead of __WARN() powerpc: Fix support for latencytop powerpc/ps3: Update ps3_defconfig powerpc/ps3: Add a sub-match id to ps3_system_bus powerpc: Add a 6xx defconfig powerpc/dma: Use the struct dma_attrs in iommu code powerpc/cell: Add support for power button of future IBM cell blades powerpc/cell: Cleanup sysreset_hack for IBM cell blades ...
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,38 @@ | ||
| Every GPIO controller node must have #gpio-cells property defined, | ||
| this information will be used to translate gpio-specifiers. | ||
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| On CPM1 devices, all ports are using slightly different register layouts. | ||
| Ports A, C and D are 16bit ports and Ports B and E are 32bit ports. | ||
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| On CPM2 devices, all ports are 32bit ports and use a common register layout. | ||
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| Required properties: | ||
| - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", | ||
| "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", | ||
| "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" | ||
| - #gpio-cells : Should be two. The first cell is the pin number and the | ||
| second cell is used to specify optional paramters (currently unused). | ||
| - gpio-controller : Marks the port as GPIO controller. | ||
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| Example of three SOC GPIO banks defined as gpio-controller nodes: | ||
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| CPM1_PIO_A: gpio-controller@950 { | ||
| #gpio-cells = <2>; | ||
| compatible = "fsl,cpm1-pario-bank-a"; | ||
| reg = <0x950 0x10>; | ||
| gpio-controller; | ||
| }; | ||
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| CPM1_PIO_B: gpio-controller@ab8 { | ||
| #gpio-cells = <2>; | ||
| compatible = "fsl,cpm1-pario-bank-b"; | ||
| reg = <0xab8 0x10>; | ||
| gpio-controller; | ||
| }; | ||
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| CPM1_PIO_E: gpio-controller@ac8 { | ||
| #gpio-cells = <2>; | ||
| compatible = "fsl,cpm1-pario-bank-e"; | ||
| reg = <0xac8 0x18>; | ||
| gpio-controller; | ||
| }; |
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|---|---|---|
| @@ -1,22 +1,37 @@ | ||
| * USB (Universal Serial Bus Controller) | ||
| Freescale QUICC Engine USB Controller | ||
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| Required properties: | ||
| - compatible : could be "qe_udc" or "fhci-hcd". | ||
| - mode : the could be "host" or "slave". | ||
| - reg : Offset and length of the register set for the device | ||
| - interrupts : <a b> where a is the interrupt number and b is a | ||
| field that represents an encoding of the sense and level | ||
| information for the interrupt. This should be encoded based on | ||
| the information in section 2) depending on the type of interrupt | ||
| controller you have. | ||
| - interrupt-parent : the phandle for the interrupt controller that | ||
| services interrupts for this device. | ||
| - compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb". | ||
| - reg : the first two cells should contain usb registers location and | ||
| length, the next two two cells should contain PRAM location and | ||
| length. | ||
| - interrupts : should contain USB interrupt. | ||
| - interrupt-parent : interrupt source phandle. | ||
| - fsl,fullspeed-clock : specifies the full speed USB clock source: | ||
| "none": clock source is disabled | ||
| "brg1" through "brg16": clock source is BRG1-BRG16, respectively | ||
| "clk1" through "clk24": clock source is CLK1-CLK24, respectively | ||
| - fsl,lowspeed-clock : specifies the low speed USB clock source: | ||
| "none": clock source is disabled | ||
| "brg1" through "brg16": clock source is BRG1-BRG16, respectively | ||
| "clk1" through "clk24": clock source is CLK1-CLK24, respectively | ||
| - hub-power-budget : USB power budget for the root hub, in mA. | ||
| - gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP, | ||
| USBRN, SPEED (optional), and POWER (optional). | ||
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| Example(slave): | ||
| usb@6c0 { | ||
| compatible = "qe_udc"; | ||
| reg = <6c0 40>; | ||
| interrupts = <8b 0>; | ||
| interrupt-parent = <700>; | ||
| mode = "slave"; | ||
| }; | ||
| Example: | ||
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| usb@6c0 { | ||
| compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb"; | ||
| reg = <0x6c0 0x40 0x8b00 0x100>; | ||
| interrupts = <11>; | ||
| interrupt-parent = <&qeic>; | ||
| fsl,fullspeed-clock = "clk21"; | ||
| gpios = <&qe_pio_b 2 0 /* USBOE */ | ||
| &qe_pio_b 3 0 /* USBTP */ | ||
| &qe_pio_b 8 0 /* USBTN */ | ||
| &qe_pio_b 9 0 /* USBRP */ | ||
| &qe_pio_b 11 0 /* USBRN */ | ||
| &qe_pio_e 20 0 /* SPEED */ | ||
| &qe_pio_e 21 0 /* POWER */>; | ||
| }; |
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Documentation/powerpc/dts-bindings/fsl/mcu-mpc8349emitx.txt
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| Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU) | ||
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| Required properties: | ||
| - compatible : "fsl,<mcu-chip>-<board>", "fsl,mcu-mpc8349emitx". | ||
| - reg : should specify I2C address (0x0a). | ||
| - #gpio-cells : should be 2. | ||
| - gpio-controller : should be present. | ||
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| Example: | ||
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| mcu@0a { | ||
| #gpio-cells = <2>; | ||
| compatible = "fsl,mc9s08qg8-mpc8349emitx", | ||
| "fsl,mcu-mpc8349emitx"; | ||
| reg = <0x0a>; | ||
| gpio-controller; | ||
| }; |
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