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drm/i915: add GT number to intel_device_info
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Up to Coffeelake we could deduce this GT number from the device ID.
This doesn't seem to be the case anymore. This change reorders pciids
per GT and adds a gt field to intel_device_info. We set this field on
the following platforms :

   - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL

Before & After :

$ modinfo drivers/gpu/drm/i915/i915.ko | grep ^alias | wc -l
209

v2: Add SNB & IVB (Chris)

v3: Fix compilation error in early-quirks (Lionel)

v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-2-lionel.g.landwerlin@intel.com
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Lionel Landwerlin committed Sep 1, 2017
1 parent e8f345e commit 0890540
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Showing 3 changed files with 246 additions and 100 deletions.
1 change: 1 addition & 0 deletions drivers/gpu/drm/i915/i915_drv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -860,6 +860,7 @@ struct intel_device_info {
u8 gen;
u16 gen_mask;
enum intel_platform platform;
u8 gt; /* GT number, 0 if undefined */
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
#define DEFINE_FLAG(name) u8 name:1
Expand Down
193 changes: 150 additions & 43 deletions drivers/gpu/drm/i915/i915_pci.c
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Original file line number Diff line number Diff line change
Expand Up @@ -224,15 +224,34 @@ static const struct intel_device_info intel_ironlake_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS

static const struct intel_device_info intel_sandybridge_d_info = {
GEN6_FEATURES,
.platform = INTEL_SANDYBRIDGE,
#define SNB_D_PLATFORM \
GEN6_FEATURES, \
.platform = INTEL_SANDYBRIDGE

static const struct intel_device_info intel_sandybridge_d_gt1_info = {
SNB_D_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_sandybridge_m_info = {
GEN6_FEATURES,
.platform = INTEL_SANDYBRIDGE,
.is_mobile = 1,
static const struct intel_device_info intel_sandybridge_d_gt2_info = {
SNB_D_PLATFORM,
.gt = 2,
};

#define SNB_M_PLATFORM \
GEN6_FEATURES, \
.platform = INTEL_SANDYBRIDGE, \
.is_mobile = 1


static const struct intel_device_info intel_sandybridge_m_gt1_info = {
SNB_M_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_sandybridge_m_gt2_info = {
SNB_M_PLATFORM,
.gt = 2,
};

#define GEN7_FEATURES \
Expand All @@ -249,22 +268,41 @@ static const struct intel_device_info intel_sandybridge_m_info = {
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS

static const struct intel_device_info intel_ivybridge_d_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
.has_l3_dpf = 1,
#define IVB_D_PLATFORM \
GEN7_FEATURES, \
.platform = INTEL_IVYBRIDGE, \
.has_l3_dpf = 1

static const struct intel_device_info intel_ivybridge_d_gt1_info = {
IVB_D_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
.is_mobile = 1,
.has_l3_dpf = 1,
static const struct intel_device_info intel_ivybridge_d_gt2_info = {
IVB_D_PLATFORM,
.gt = 2,
};

#define IVB_M_PLATFORM \
GEN7_FEATURES, \
.platform = INTEL_IVYBRIDGE, \
.is_mobile = 1, \
.has_l3_dpf = 1

static const struct intel_device_info intel_ivybridge_m_gt1_info = {
IVB_M_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_ivybridge_m_gt2_info = {
IVB_M_PLATFORM,
.gt = 2,
};

static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.platform = INTEL_IVYBRIDGE,
.gt = 2,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
Expand Down Expand Up @@ -299,10 +337,24 @@ static const struct intel_device_info intel_valleyview_info = {
.has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1

static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES,
.platform = INTEL_HASWELL,
.has_l3_dpf = 1,
#define HSW_PLATFORM \
HSW_FEATURES, \
.platform = INTEL_HASWELL, \
.has_l3_dpf = 1

static const struct intel_device_info intel_haswell_gt1_info = {
HSW_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_haswell_gt2_info = {
HSW_PLATFORM,
.gt = 2,
};

static const struct intel_device_info intel_haswell_gt3_info = {
HSW_PLATFORM,
.gt = 3,
};

#define BDW_FEATURES \
Expand All @@ -318,12 +370,27 @@ static const struct intel_device_info intel_haswell_info = {
.gen = 8, \
.platform = INTEL_BROADWELL

static const struct intel_device_info intel_broadwell_info = {
static const struct intel_device_info intel_broadwell_gt1_info = {
BDW_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_broadwell_gt2_info = {
BDW_PLATFORM,
.gt = 2,
};

static const struct intel_device_info intel_broadwell_rsvd_info = {
BDW_PLATFORM,
.gt = 3,
/* According to the device ID those devices are GT3, they were
* previously treated as not GT3, keep it like that.
*/
};

static const struct intel_device_info intel_broadwell_gt3_info = {
BDW_PLATFORM,
.gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

Expand Down Expand Up @@ -358,13 +425,29 @@ static const struct intel_device_info intel_cherryview_info = {
.has_guc = 1, \
.ddb_size = 896

static const struct intel_device_info intel_skylake_info = {
static const struct intel_device_info intel_skylake_gt1_info = {
SKL_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_skylake_gt3_info = {
static const struct intel_device_info intel_skylake_gt2_info = {
SKL_PLATFORM,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
.gt = 2,
};

#define SKL_GT3_PLUS_PLATFORM \
SKL_PLATFORM, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING


static const struct intel_device_info intel_skylake_gt3_info = {
SKL_GT3_PLUS_PLATFORM,
.gt = 3,
};

static const struct intel_device_info intel_skylake_gt4_info = {
SKL_GT3_PLUS_PLATFORM,
.gt = 4,
};

#define GEN9_LP_FEATURES \
Expand Down Expand Up @@ -415,12 +498,19 @@ static const struct intel_device_info intel_geminilake_info = {
.has_guc = 1, \
.ddb_size = 896

static const struct intel_device_info intel_kabylake_info = {
static const struct intel_device_info intel_kabylake_gt1_info = {
KBL_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_kabylake_gt2_info = {
KBL_PLATFORM,
.gt = 2,
};

static const struct intel_device_info intel_kabylake_gt3_info = {
KBL_PLATFORM,
.gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

Expand All @@ -433,20 +523,28 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
.has_guc = 1, \
.ddb_size = 896

static const struct intel_device_info intel_coffeelake_info = {
static const struct intel_device_info intel_coffeelake_gt1_info = {
CFL_PLATFORM,
.gt = 1,
};

static const struct intel_device_info intel_coffeelake_gt2_info = {
CFL_PLATFORM,
.gt = 2,
};

static const struct intel_device_info intel_coffeelake_gt3_info = {
CFL_PLATFORM,
.gt = 3,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

static const struct intel_device_info intel_cannonlake_info = {
static const struct intel_device_info intel_cannonlake_gt2_info = {
BDW_FEATURES,
.is_alpha_support = 1,
.platform = INTEL_CANNONLAKE,
.gen = 10,
.gt = 2,
.ddb_size = 1024,
.has_csr = 1,
.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
Expand Down Expand Up @@ -475,31 +573,40 @@ static const struct pci_device_id pciidlist[] = {
INTEL_PINEVIEW_IDS(&intel_pineview_info),
INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
INTEL_HSW_IDS(&intel_haswell_info),
INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
INTEL_VLV_IDS(&intel_valleyview_info),
INTEL_BDW_GT12_IDS(&intel_broadwell_info),
INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
INTEL_CHV_IDS(&intel_cherryview_info),
INTEL_SKL_GT1_IDS(&intel_skylake_info),
INTEL_SKL_GT2_IDS(&intel_skylake_info),
INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
INTEL_BXT_IDS(&intel_broxton_info),
INTEL_GLK_IDS(&intel_geminilake_info),
INTEL_KBL_GT1_IDS(&intel_kabylake_info),
INTEL_KBL_GT2_IDS(&intel_kabylake_info),
INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
INTEL_CFL_S_IDS(&intel_coffeelake_info),
INTEL_CFL_H_IDS(&intel_coffeelake_info),
INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info),
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
Expand Down
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