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drm/i915: Work around GCC anonymous union initialization bug
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GCC 4.4 can't cope with anonymous union initializers which seems to be a
bug in that version (see the Reference) and is fixed since GCC version
4.6. A workaround which is also used elsewhere in the kernel for the
same purpose is to wrap the initialization in curly braces, so do the
same here.

Fixes: b5565a2 ("drm/i915/bxt, glk: Give a proper name to the power well struct phy field")
Reference: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170814151530.24154-1-imre.deak@intel.com
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Imre Deak committed Aug 15, 2017
1 parent baa68f6 commit 0a44594
Showing 1 changed file with 54 additions and 24 deletions.
78 changes: 54 additions & 24 deletions drivers/gpu/drm/i915/intel_runtime_pm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1920,7 +1920,9 @@ static struct i915_power_well hsw_power_wells[] = {
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
.hsw.has_vga = true,
{
.hsw.has_vga = true,
},
},
};

Expand All @@ -1937,8 +1939,10 @@ static struct i915_power_well bdw_power_wells[] = {
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
{
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
},
},
};

Expand Down Expand Up @@ -2080,7 +2084,9 @@ static struct i915_power_well skl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
.hsw.has_fuses = true,
{
.hsw.has_fuses = true,
},
},
{
.name = "MISC IO power well",
Expand All @@ -2100,9 +2106,11 @@ static struct i915_power_well skl_power_wells[] = {
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
{
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
},
},
{
.name = "DDI A/E IO power well",
Expand Down Expand Up @@ -2143,7 +2151,9 @@ static struct i915_power_well bxt_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
.hsw.has_fuses = true,
{
.hsw.has_fuses = true,
},
},
{
.name = "DC off",
Expand All @@ -2156,23 +2166,29 @@ static struct i915_power_well bxt_power_wells[] = {
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
{
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
},
},
{
.name = "dpio-common-a",
.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_A,
.bxt.phy = DPIO_PHY1,
{
.bxt.phy = DPIO_PHY1,
},
},
{
.name = "dpio-common-bc",
.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_BC,
.bxt.phy = DPIO_PHY0,
{
.bxt.phy = DPIO_PHY0,
},
},
};

Expand All @@ -2190,7 +2206,9 @@ static struct i915_power_well glk_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
.hsw.has_fuses = true,
{
.hsw.has_fuses = true,
},
},
{
.name = "DC off",
Expand All @@ -2203,30 +2221,38 @@ static struct i915_power_well glk_power_wells[] = {
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
{
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
},
},
{
.name = "dpio-common-a",
.domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_A,
.bxt.phy = DPIO_PHY1,
{
.bxt.phy = DPIO_PHY1,
},
},
{
.name = "dpio-common-b",
.domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DPIO_CMN_BC,
.bxt.phy = DPIO_PHY0,
{
.bxt.phy = DPIO_PHY0,
},
},
{
.name = "dpio-common-c",
.domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = GLK_DPIO_CMN_C,
.bxt.phy = DPIO_PHY2,
{
.bxt.phy = DPIO_PHY2,
},
},
{
.name = "AUX A",
Expand Down Expand Up @@ -2280,7 +2306,9 @@ static struct i915_power_well cnl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
.hsw.has_fuses = true,
{
.hsw.has_fuses = true,
},
},
{
.name = "AUX A",
Expand Down Expand Up @@ -2317,9 +2345,11 @@ static struct i915_power_well cnl_power_wells[] = {
.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_2,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
{
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
.hsw.has_fuses = true,
},
},
{
.name = "DDI A IO power well",
Expand Down

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