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Merge remote-tracking branch 'airlied/drm-next' into HEAD
Backmerge drm-next because the conflict between Ander's atomic fixes for 4.2 and Maartens future work are getting to unwielding to handle. Conflicts: drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i915/intel_ringbuffer.h Just always take ours, same as git merge -X ours, but done by hand because I didn't trust git: It's confusing that it doesn't show any conflicts in the merge diff at all. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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Qualcomm Technologies Inc. adreno/snapdragon DSI output | ||
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DSI Controller: | ||
Required properties: | ||
- compatible: | ||
* "qcom,mdss-dsi-ctrl" | ||
- reg: Physical base address and length of the registers of controller | ||
- reg-names: The names of register regions. The following regions are required: | ||
* "dsi_ctrl" | ||
- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should | ||
be 0 or 1, since we have 2 DSI controllers at most for now. | ||
- interrupts: The interrupt signal from the DSI block. | ||
- power-domains: Should be <&mmcc MDSS_GDSC>. | ||
- clocks: device clocks | ||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. | ||
- clock-names: the following clocks are required: | ||
* "bus_clk" | ||
* "byte_clk" | ||
* "core_clk" | ||
* "core_mmss_clk" | ||
* "iface_clk" | ||
* "mdp_core_clk" | ||
* "pixel_clk" | ||
- vdd-supply: phandle to vdd regulator device node | ||
- vddio-supply: phandle to vdd-io regulator device node | ||
- vdda-supply: phandle to vdda regulator device node | ||
- qcom,dsi-phy: phandle to DSI PHY device node | ||
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||
Optional properties: | ||
- panel@0: Node of panel connected to this DSI controller. | ||
See files in Documentation/devicetree/bindings/panel/ for each supported | ||
panel. | ||
- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is | ||
driving a panel which needs 2 DSI links. | ||
- qcom,master-panel: Boolean value indicating if the DSI controller is driving | ||
the master link of the 2-DSI panel. | ||
- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is | ||
driving a 2-DSI panel whose 2 links need receive command simultaneously. | ||
- interrupt-parent: phandle to the MDP block if the interrupt signal is routed | ||
through MDP block | ||
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||
DSI PHY: | ||
Required properties: | ||
- compatible: Could be the following | ||
* "qcom,dsi-phy-28nm-hpm" | ||
* "qcom,dsi-phy-28nm-lp" | ||
- reg: Physical base address and length of the registers of PLL, PHY and PHY | ||
regulator | ||
- reg-names: The names of register regions. The following regions are required: | ||
* "dsi_pll" | ||
* "dsi_phy" | ||
* "dsi_phy_regulator" | ||
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should | ||
be 0 or 1, since we have 2 DSI PHYs at most for now. | ||
- power-domains: Should be <&mmcc MDSS_GDSC>. | ||
- clocks: device clocks | ||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. | ||
- clock-names: the following clocks are required: | ||
* "iface_clk" | ||
- vddio-supply: phandle to vdd-io regulator device node | ||
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||
Example: | ||
mdss_dsi0: qcom,mdss_dsi@fd922800 { | ||
compatible = "qcom,mdss-dsi-ctrl"; | ||
qcom,dsi-host-index = <0>; | ||
interrupt-parent = <&mdss_mdp>; | ||
interrupts = <4 0>; | ||
reg-names = "dsi_ctrl"; | ||
reg = <0xfd922800 0x200>; | ||
power-domains = <&mmcc MDSS_GDSC>; | ||
clock-names = | ||
"bus_clk", | ||
"byte_clk", | ||
"core_clk", | ||
"core_mmss_clk", | ||
"iface_clk", | ||
"mdp_core_clk", | ||
"pixel_clk"; | ||
clocks = | ||
<&mmcc MDSS_AXI_CLK>, | ||
<&mmcc MDSS_BYTE0_CLK>, | ||
<&mmcc MDSS_ESC0_CLK>, | ||
<&mmcc MMSS_MISC_AHB_CLK>, | ||
<&mmcc MDSS_AHB_CLK>, | ||
<&mmcc MDSS_MDP_CLK>, | ||
<&mmcc MDSS_PCLK0_CLK>; | ||
vdda-supply = <&pma8084_l2>; | ||
vdd-supply = <&pma8084_l22>; | ||
vddio-supply = <&pma8084_l12>; | ||
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qcom,dsi-phy = <&mdss_dsi_phy0>; | ||
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qcom,dual-panel-mode; | ||
qcom,master-panel; | ||
qcom,sync-dual-panel; | ||
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panel: panel@0 { | ||
compatible = "sharp,lq101r1sx01"; | ||
reg = <0>; | ||
link2 = <&secondary>; | ||
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power-supply = <...>; | ||
backlight = <...>; | ||
}; | ||
}; | ||
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mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 { | ||
compatible = "qcom,dsi-phy-28nm-hpm"; | ||
qcom,dsi-phy-index = <0>; | ||
reg-names = | ||
"dsi_pll", | ||
"dsi_phy", | ||
"dsi_phy_regulator"; | ||
reg = <0xfd922a00 0xd4>, | ||
<0xfd922b00 0x2b0>, | ||
<0xfd922d80 0x7b>; | ||
clock-names = "iface_clk"; | ||
clocks = <&mmcc MDSS_AHB_CLK>; | ||
vddio-supply = <&pma8084_l12>; | ||
}; |
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Qualcomm Technologies Inc. adreno/snapdragon eDP output | ||
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||
Required properties: | ||
- compatible: | ||
* "qcom,mdss-edp" | ||
- reg: Physical base address and length of the registers of controller and PLL | ||
- reg-names: The names of register regions. The following regions are required: | ||
* "edp" | ||
* "pll_base" | ||
- interrupts: The interrupt signal from the eDP block. | ||
- power-domains: Should be <&mmcc MDSS_GDSC>. | ||
- clocks: device clocks | ||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. | ||
- clock-names: the following clocks are required: | ||
* "core_clk" | ||
* "iface_clk" | ||
* "mdp_core_clk" | ||
* "pixel_clk" | ||
* "link_clk" | ||
- #clock-cells: The value should be 1. | ||
- vdda-supply: phandle to vdda regulator device node | ||
- lvl-vdd-supply: phandle to regulator device node which is used to supply power | ||
to HPD receiving chip | ||
- panel-en-gpios: GPIO pin to supply power to panel. | ||
- panel-hpd-gpios: GPIO pin used for eDP hpd. | ||
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Optional properties: | ||
- interrupt-parent: phandle to the MDP block if the interrupt signal is routed | ||
through MDP block | ||
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||
Example: | ||
mdss_edp: qcom,mdss_edp@fd923400 { | ||
compatible = "qcom,mdss-edp"; | ||
reg-names = | ||
"edp", | ||
"pll_base"; | ||
reg = <0xfd923400 0x700>, | ||
<0xfd923a00 0xd4>; | ||
interrupt-parent = <&mdss_mdp>; | ||
interrupts = <12 0>; | ||
power-domains = <&mmcc MDSS_GDSC>; | ||
clock-names = | ||
"core_clk", | ||
"pixel_clk", | ||
"iface_clk", | ||
"link_clk", | ||
"mdp_core_clk"; | ||
clocks = | ||
<&mmcc MDSS_EDPAUX_CLK>, | ||
<&mmcc MDSS_EDPPIXEL_CLK>, | ||
<&mmcc MDSS_AHB_CLK>, | ||
<&mmcc MDSS_EDPLINK_CLK>, | ||
<&mmcc MDSS_MDP_CLK>; | ||
#clock-cells = <1>; | ||
vdda-supply = <&pma8084_l12>; | ||
lvl-vdd-supply = <&lvl_vreg>; | ||
panel-en-gpios = <&tlmm 137 0>; | ||
panel-hpd-gpios = <&tlmm 103 0>; | ||
}; |
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7 changes: 7 additions & 0 deletions
7
Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt
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HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel | ||
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Required properties: | ||
- compatible: should be "hannstar,hsd100pxn1" | ||
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This binding is compatible with the simple-panel binding, which is specified | ||
in simple-panel.txt in this directory. |
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LG 7" (800x480 pixels) TFT LCD panel | ||
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Required properties: | ||
- compatible: should be "lg,lb070wv8" | ||
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This binding is compatible with the simple-panel binding, which is specified | ||
in simple-panel.txt in this directory. |
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Device-Tree bindings for Samsung Exynos SoC mobile image compressor (MIC) | ||
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MIC (mobile image compressor) resides between decon and mipi dsi. Mipi dsi is | ||
not capable to transfer high resoltuion frame data as decon can send. MIC | ||
solves this problem by compressing the frame data by 1/2 before it is | ||
transferred through mipi dsi. The compressed frame data must be uncompressed in | ||
the panel PCB. | ||
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Required properties: | ||
- compatible: value should be "samsung,exynos5433-mic". | ||
- reg: physical base address and length of the MIC registers set and system | ||
register of mic. | ||
- clocks: must include clock specifiers corresponding to entries in the | ||
clock-names property. | ||
- clock-names: list of clock names sorted in the same order as the clocks | ||
property. Must contain "pclk_mic0", "sclk_rgb_vclk_to_mic0". | ||
- samsung,disp-syscon: the reference node for syscon for DISP block. | ||
- ports: contains a port which is connected to decon node and dsi node. | ||
address-cells and size-cells must 1 and 0, respectively. | ||
- port: contains an endpoint node which is connected to the endpoint in the | ||
decon node or dsi node. The reg value must be 0 and 1 respectively. | ||
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Example: | ||
SoC specific DT entry: | ||
mic: mic@13930000 { | ||
compatible = "samsung,exynos5433-mic"; | ||
reg = <0x13930000 0x48>; | ||
clocks = <&cmu_disp CLK_PCLK_MIC0>, | ||
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; | ||
clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; | ||
samsung,disp-syscon = <&syscon_disp>; | ||
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ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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port@0 { | ||
reg = <0>; | ||
mic_to_decon: endpoint { | ||
remote-endpoint = <&decon_to_mic>; | ||
}; | ||
}; | ||
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port@1 { | ||
reg = <1>; | ||
mic_to_dsi: endpoint { | ||
remote-endpoint = <&dsi_to_mic>; | ||
}; | ||
}; | ||
}; | ||
}; |
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