Skip to content

Commit

Permalink
Merge tag 'drm-fixes-for-v4.7-rc5' of git://people.freedesktop.org/~a…
Browse files Browse the repository at this point in the history 
…irlied/linux

Pull drm fixes from Dave Airlie:
 "This is the drm fixes tree for 4.7-rc5.

  It's a bit larger than normal, due to fixes for production AMD Polaris
  GPUs.  We only merged support for these in 4.7-rc1 so it would be good
  if we got all the fixes into final.  The changes don't hit any other
  hardware.

  Other than the amdgpu Polaris changes:

   - A single fix for atomic modesetting WARN
   - Nouveau fix for when fbdev is disabled
   - i915 fixes for FBC on Haswell and displayport regression
   - Exynos fix for a display panel regression and some other minor changes
   - Atmel fixes for scaling and OF graph interaction
   - Allwiinner build, warning and probing fixes
   - AMD GPU non-polaris fix for num_rbs and some minor fixes

  Also I've just moved house, and my new place is Internet challenged
  due to incompetent incumbent ISPs, hopefully sorted out in a couple of
  weeks, so I might not be too responsive over the next while.  It also
  helps Daniel is on holidays for those couple of weeks as well"

* tag 'drm-fixes-for-v4.7-rc5' of git://people.freedesktop.org/~airlied/linux: (38 commits)
  drm/atomic: Make drm_atomic_legacy_backoff reset crtc->acquire_ctx
  drm/nouveau: fix for disabled fbdev emulation
  drm/i915/fbc: Disable on HSW by default for now
  drm/i915: Revert DisplayPort fast link training feature
  drm/amd/powerplay: enable clock stretch feature for polaris
  drm/amdgpu/gfx8: update golden setting for polaris10
  drm/amd/powerplay: enable avfs feature for polaris
  drm/amdgpu/atombios: add avfs struct for Polaris10/11
  drm/amd/powerplay: add avfs related define for polaris
  drm/amd/powrplay: enable stutter_mode for polaris.
  drm/amd/powerplay: disable UVD SMU handshake for MCLK.
  drm/amd/powerplay: initialize variables which were missed.
  drm/amd/powerplay: enable PowerContainment feature for polaris10/11.
  drm/amd/powerplay: need to notify system bios pcie device ready
  drm/amd/powerplay: fix bug that function parameter was incorect.
  drm/amd/powerplay: fix logic error.
  drm: atmel-hlcdc: Fix OF graph parsing
  drm: atmel-hlcdc: actually disable scaling when no scaling is required
  drm/amdgpu: initialize amdgpu_cgs_acpi_eval_object result value
  drm/amdgpu: precedence bug in amdgpu_device_init()
  ...
  • Loading branch information
Linus Torvalds committed Jun 24, 2016
2 parents 75befb3 + 81e257e commit 0bf0ea4
Show file tree
Hide file tree
Showing 40 changed files with 598 additions and 256 deletions.
2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -909,7 +909,7 @@ static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
struct cgs_acpi_method_argument *argument = NULL;
uint32_t i, count;
acpi_status status;
int result;
int result = 0;
uint32_t func_no = 0xFFFFFFFF;

handle = ACPI_HANDLE(&adev->pdev->dev);
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1535,7 +1535,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* Post card if necessary */
if (!amdgpu_card_posted(adev) ||
(adev->virtualization.is_virtual &&
!adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN)) {
!(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) {
if (!adev->bios) {
dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
return -EINVAL;
Expand Down
3 changes: 2 additions & 1 deletion drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -447,7 +447,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
dev_info.max_memory_clock = adev->pm.default_mclk * 10;
}
dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
dev_info.num_rb_pipes = adev->gfx.config.num_rbs;
dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
adev->gfx.config.max_shader_engines;
dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
dev_info._pad = 0;
dev_info.ids_flags = 0;
Expand Down
28 changes: 13 additions & 15 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -270,30 +270,28 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
enum amd_pm_state_type state = 0;
long idx;
unsigned long idx;
int ret;

if (strlen(buf) == 1)
adev->pp_force_state_enabled = false;
else {
ret = kstrtol(buf, 0, &idx);
else if (adev->pp_enabled) {
struct pp_states_info data;

if (ret) {
ret = kstrtoul(buf, 0, &idx);
if (ret || idx >= ARRAY_SIZE(data.states)) {
count = -EINVAL;
goto fail;
}

if (adev->pp_enabled) {
struct pp_states_info data;
amdgpu_dpm_get_pp_num_states(adev, &data);
state = data.states[idx];
/* only set user selected power states */
if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
state != POWER_STATE_TYPE_DEFAULT) {
amdgpu_dpm_dispatch_task(adev,
AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
adev->pp_force_state_enabled = true;
}
amdgpu_dpm_get_pp_num_states(adev, &data);
state = data.states[idx];
/* only set user selected power states */
if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
state != POWER_STATE_TYPE_DEFAULT) {
amdgpu_dpm_dispatch_task(adev,
AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
adev->pp_force_state_enabled = true;
}
}
fail:
Expand Down
3 changes: 2 additions & 1 deletion drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -297,7 +297,8 @@ static const u32 polaris11_golden_common_all[] =
static const u32 golden_settings_polaris10_a11[] =
{
mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208,
mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
mmCB_HW_CONTROL_2, 0, 0x0f000000,
mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
mmDB_DEBUG2, 0xf00fffff, 0x00000400,
mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
Expand Down
72 changes: 72 additions & 0 deletions drivers/gpu/drm/amd/include/atombios.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5538,6 +5538,78 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5
ULONG ulReserved[12];
}ATOM_ASIC_PROFILING_INFO_V3_5;

/* for Polars10/11 AVFS parameters */
typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6
{
ATOM_COMMON_TABLE_HEADER asHeader;
ULONG ulMaxVddc;
ULONG ulMinVddc;
USHORT usLkgEuseIndex;
UCHAR ucLkgEfuseBitLSB;
UCHAR ucLkgEfuseLength;
ULONG ulLkgEncodeLn_MaxDivMin;
ULONG ulLkgEncodeMax;
ULONG ulLkgEncodeMin;
EFUSE_LINEAR_FUNC_PARAM sRoFuse;
ULONG ulEvvDefaultVddc;
ULONG ulEvvNoCalcVddc;
ULONG ulSpeed_Model;
ULONG ulSM_A0;
ULONG ulSM_A1;
ULONG ulSM_A2;
ULONG ulSM_A3;
ULONG ulSM_A4;
ULONG ulSM_A5;
ULONG ulSM_A6;
ULONG ulSM_A7;
UCHAR ucSM_A0_sign;
UCHAR ucSM_A1_sign;
UCHAR ucSM_A2_sign;
UCHAR ucSM_A3_sign;
UCHAR ucSM_A4_sign;
UCHAR ucSM_A5_sign;
UCHAR ucSM_A6_sign;
UCHAR ucSM_A7_sign;
ULONG ulMargin_RO_a;
ULONG ulMargin_RO_b;
ULONG ulMargin_RO_c;
ULONG ulMargin_fixed;
ULONG ulMargin_Fmax_mean;
ULONG ulMargin_plat_mean;
ULONG ulMargin_Fmax_sigma;
ULONG ulMargin_plat_sigma;
ULONG ulMargin_DC_sigma;
ULONG ulLoadLineSlop;
ULONG ulaTDClimitPerDPM[8];
ULONG ulaNoCalcVddcPerDPM[8];
ULONG ulAVFS_meanNsigma_Acontant0;
ULONG ulAVFS_meanNsigma_Acontant1;
ULONG ulAVFS_meanNsigma_Acontant2;
USHORT usAVFS_meanNsigma_DC_tol_sigma;
USHORT usAVFS_meanNsigma_Platform_mean;
USHORT usAVFS_meanNsigma_Platform_sigma;
ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;
ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;
ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;
ULONG ulGB_VDROOP_TABLE_CKSON_a0;
ULONG ulGB_VDROOP_TABLE_CKSON_a1;
ULONG ulGB_VDROOP_TABLE_CKSON_a2;
ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2;
ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;
ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;
USHORT usAVFSGB_FUSE_TABLE_CKSON_m2;
ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;
USHORT usMaxVoltage_0_25mv;
UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF;
UCHAR ucEnableGB_VDROOP_TABLE_CKSON;
UCHAR ucEnableGB_FUSE_TABLE_CKSOFF;
UCHAR ucEnableGB_FUSE_TABLE_CKSON;
USHORT usPSM_Age_ComFactor;
UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage;
UCHAR ucReserved;
}ATOM_ASIC_PROFILING_INFO_V3_6;


typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
ULONG ulMaxSclkFreq;
Expand Down
2 changes: 2 additions & 0 deletions drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -633,6 +633,8 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;

data->force_pcie_gen = PP_PCIEGenInvalid;

if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
Expand Down
6 changes: 5 additions & 1 deletion drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -306,10 +306,14 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
{
PHM_FUNC_CHECK(hwmgr);

if (hwmgr->hwmgr_func->store_cc6_data == NULL)
if (display_config == NULL)
return -EINVAL;

hwmgr->display_config = *display_config;

if (hwmgr->hwmgr_func->store_cc6_data == NULL)
return -EINVAL;

/* to do pass other display configuration in furture */

if (hwmgr->hwmgr_func->store_cc6_data)
Expand Down
Loading

0 comments on commit 0bf0ea4

Please sign in to comment.