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Merge branches 'acpi-x86', 'acpi-cppc' and 'acpi-soc'
* acpi-x86: x86: ACPI: make variable names clearer in acpi_parse_madt_lapic_entries() x86: ACPI: remove extraneous white space after semicolon * acpi-cppc: ACPI / CPPC: Support PCC with interrupt flag ACPI / CPPC: Add prefix cppc to cpudata structure name ACPI / CPPC: Add support for functional fixed hardware address ACPI / CPPC: Don't return on CPPC probe failure ACPI / CPPC: Allow build with ACPI_CPU_FREQ_PSS config ACPI / CPPC: check for error bit in PCC status field ACPI / CPPC: move all PCC related information into pcc_data ACPI / CPPC: add sysfs support to compute delivered performance ACPI / CPPC: set a non-zero value for transition_latency ACPI / CPPC: support for batching CPPC requests ACPI / CPPC: acquire pcc_lock only while accessing PCC subspace ACPI / CPPC: restructure read/writes for efficient sys mapped reg ops mailbox: pcc: Support HW-Reduced Communication Subspace type 2 * acpi-soc: ACPI / APD: constify local structures ACPI / APD: Add device HID for Vulcan SPI controller
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Original file line number | Diff line number | Diff line change |
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/* | ||
* cppc_msr.c: MSR Interface for CPPC | ||
* Copyright (c) 2016, Intel Corporation. | ||
* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms and conditions of the GNU General Public License, | ||
* version 2, as published by the Free Software Foundation. | ||
* | ||
* This program is distributed in the hope it will be useful, but WITHOUT | ||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
* more details. | ||
* | ||
*/ | ||
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#include <acpi/cppc_acpi.h> | ||
#include <asm/msr.h> | ||
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/* Refer to drivers/acpi/cppc_acpi.c for the description of functions */ | ||
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bool cpc_ffh_supported(void) | ||
{ | ||
return true; | ||
} | ||
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int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) | ||
{ | ||
int err; | ||
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err = rdmsrl_safe_on_cpu(cpunum, reg->address, val); | ||
if (!err) { | ||
u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, | ||
reg->bit_offset); | ||
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*val &= mask; | ||
*val >>= reg->bit_offset; | ||
} | ||
return err; | ||
} | ||
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int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) | ||
{ | ||
u64 rd_val; | ||
int err; | ||
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err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val); | ||
if (!err) { | ||
u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, | ||
reg->bit_offset); | ||
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val <<= reg->bit_offset; | ||
val &= mask; | ||
rd_val &= ~mask; | ||
rd_val |= val; | ||
err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val); | ||
} | ||
return err; | ||
} |
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