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Merge tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32…
…xx into next/dt Merge "NXP LPC32xx device tree updates for v4.7" from Vladimir Zapolskiy: This includes a few functional changes: * new representation of MIC, SIC1 and SIC2 interrupt controllers, * disabled by default SPI1, SPI2, SSP0 and SSP1 SPI controllers in shared lpc32xx.dtsi file, * added clock sources for SPI1 and SPI2, * set default clock rate of HCLK PLL to main osc rate multiplied by 16. Also there are some non-functional changes: * flatten board DTS files by exploiting device node labels, * add 'partitions' device node for NAND SLC / MTD OF, * correct Atmel vendor prefix to describe on board AT24 EEPROMs, * rename board DTS files by adding SoC name prefix. Since now DTS files of LPC32xx boards match "^lpc32[2345]0-" pattern. * tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx: ARM: dts: lpc32xx: phy3250: add SoC name prefix to board dts file ARM: dts: lpc32xx: phy3250: add NAND partitions device node ARM: dts: lpc32xx: phy3250: avoid extension of device nodes by absolute path ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file ARM: dts: lpc32xx: ea3250: fix Atmel at24 eeprom vendor ARM: dts: lpc32xx: ea3250: add NAND partitions device node ARM: dts: lpc32xx: ea3250: avoid extension of device nodes by absolute path ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC dt-bindings: interrupt-controllers: add description of SIC1 and SIC2 ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default ARM: dts: phy3250: enable ssp0 ARM: dts: lpc32xx: add clock properties to spi nodes ARM: dts: lpc32xx: set default clock rate of HCLK PLL
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Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,38 +1,60 @@ | ||
| * NXP LPC32xx Main Interrupt Controller | ||
| (MIC, including SIC1 and SIC2 secondary controllers) | ||
| * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "nxp,lpc3220-mic" | ||
| - interrupt-controller: Identifies the node as an interrupt controller. | ||
| - interrupt-parent: Empty for the interrupt controller itself | ||
| - #interrupt-cells: The number of cells to define the interrupts. Should be 2. | ||
| The first cell is the IRQ number | ||
| The second cell is used to specify mode: | ||
| 1 = low-to-high edge triggered | ||
| 2 = high-to-low edge triggered | ||
| 4 = active high level-sensitive | ||
| 8 = active low level-sensitive | ||
| Default for internal sources should be set to 4 (active high). | ||
| - reg: Should contain MIC registers location and length | ||
| - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". | ||
| - reg: should contain IC registers location and length. | ||
| - interrupt-controller: identifies the node as an interrupt controller. | ||
| - #interrupt-cells: the number of cells to define an interrupt, should be 2. | ||
| The first cell is the IRQ number, the second cell is used to specify | ||
| one of the supported IRQ types: | ||
| IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, | ||
| IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, | ||
| IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, | ||
| IRQ_TYPE_LEVEL_LOW = active low level-sensitive. | ||
| Reset value is IRQ_TYPE_LEVEL_LOW. | ||
|
|
||
| Optional properties: | ||
| - interrupt-parent: empty for MIC interrupt controller, link to parent | ||
| MIC interrupt controller for SIC1 and SIC2 | ||
| - interrupts: empty for MIC interrupt controller, cascaded MIC | ||
| hardware interrupts for SIC1 and SIC2 | ||
|
|
||
| Examples: | ||
| /* | ||
| * MIC | ||
| */ | ||
|
|
||
| /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ | ||
| mic: interrupt-controller@40008000 { | ||
| compatible = "nxp,lpc3220-mic"; | ||
| reg = <0x40008000 0x4000>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <2>; | ||
| }; | ||
|
|
||
| sic1: interrupt-controller@4000c000 { | ||
| compatible = "nxp,lpc3220-sic"; | ||
| reg = <0x4000c000 0x4000>; | ||
| interrupt-controller; | ||
| interrupt-parent; | ||
| #interrupt-cells = <2>; | ||
| reg = <0x40008000 0xC000>; | ||
|
|
||
| interrupt-parent = <&mic>; | ||
| interrupts = <0 IRQ_TYPE_LEVEL_LOW>, | ||
| <30 IRQ_TYPE_LEVEL_LOW>; | ||
| }; | ||
|
|
||
| /* | ||
| * ADC | ||
| */ | ||
| sic2: interrupt-controller@40010000 { | ||
| compatible = "nxp,lpc3220-sic"; | ||
| reg = <0x40010000 0x4000>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <2>; | ||
|
|
||
| interrupt-parent = <&mic>; | ||
| interrupts = <1 IRQ_TYPE_LEVEL_LOW>, | ||
| <31 IRQ_TYPE_LEVEL_LOW>; | ||
| }; | ||
|
|
||
| /* ADC */ | ||
| adc@40048000 { | ||
| compatible = "nxp,lpc3220-adc"; | ||
| reg = <0x40048000 0x1000>; | ||
| interrupt-parent = <&mic>; | ||
| interrupts = <39 4>; | ||
| interrupt-parent = <&sic1>; | ||
| interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,226 @@ | ||
| /* | ||
| * PHYTEC phyCORE-LPC3250 board | ||
| * | ||
| * Copyright 2012 Roland Stigge <stigge@antcom.de> | ||
| * | ||
| * The code contained herein is licensed under the GNU General Public | ||
| * License. You may obtain a copy of the GNU General Public License | ||
| * Version 2 or later at the following locations: | ||
| * | ||
| * http://www.opensource.org/licenses/gpl-license.html | ||
| * http://www.gnu.org/copyleft/gpl.html | ||
| */ | ||
|
|
||
| /dts-v1/; | ||
| #include "lpc32xx.dtsi" | ||
|
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||
| / { | ||
| model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; | ||
| compatible = "phytec,phy3250", "nxp,lpc3250"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
|
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||
| memory { | ||
| device_type = "memory"; | ||
| reg = <0x80000000 0x4000000>; | ||
| }; | ||
|
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||
| regulators { | ||
| backlight_reg: regulator@0 { | ||
| compatible = "regulator-fixed"; | ||
| regulator-name = "backlight_reg"; | ||
| regulator-min-microvolt = <1800000>; | ||
| regulator-max-microvolt = <1800000>; | ||
| gpio = <&gpio 5 4 0>; | ||
| enable-active-high; | ||
| regulator-boot-on; | ||
| }; | ||
|
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||
| lcd_reg: regulator@1 { | ||
| compatible = "regulator-fixed"; | ||
| regulator-name = "lcd_reg"; | ||
| regulator-min-microvolt = <1800000>; | ||
| regulator-max-microvolt = <1800000>; | ||
| gpio = <&gpio 5 0 0>; | ||
| enable-active-high; | ||
| regulator-boot-on; | ||
| }; | ||
|
|
||
| sd_reg: regulator@2 { | ||
| compatible = "regulator-fixed"; | ||
| regulator-name = "sd_reg"; | ||
| regulator-min-microvolt = <1800000>; | ||
| regulator-max-microvolt = <1800000>; | ||
| gpio = <&gpio 5 5 0>; | ||
| enable-active-high; | ||
| }; | ||
| }; | ||
|
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||
| leds { | ||
| compatible = "gpio-leds"; | ||
|
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||
| led0 { /* red */ | ||
| gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ | ||
| default-state = "off"; | ||
| }; | ||
|
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||
| led1 { /* green */ | ||
| gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ | ||
| linux,default-trigger = "heartbeat"; | ||
| }; | ||
| }; | ||
| }; | ||
|
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||
| &clcd { | ||
| status = "okay"; | ||
| }; | ||
|
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||
| &i2c1 { | ||
| clock-frequency = <100000>; | ||
|
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||
| uda1380: uda1380@18 { | ||
| compatible = "nxp,uda1380"; | ||
| reg = <0x18>; | ||
| power-gpio = <&gpio 0x59 0>; | ||
| reset-gpio = <&gpio 0x51 0>; | ||
| dac-clk = "wspll"; | ||
| }; | ||
|
|
||
| pcf8563: rtc@51 { | ||
| compatible = "nxp,pcf8563"; | ||
| reg = <0x51>; | ||
| }; | ||
| }; | ||
|
|
||
| &i2c2 { | ||
| clock-frequency = <100000>; | ||
| }; | ||
|
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||
| &i2cusb { | ||
| clock-frequency = <100000>; | ||
|
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||
| isp1301: usb-transceiver@2c { | ||
| compatible = "nxp,isp1301"; | ||
| reg = <0x2c>; | ||
| }; | ||
| }; | ||
|
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||
| &key { | ||
| keypad,num-rows = <1>; | ||
| keypad,num-columns = <1>; | ||
| nxp,debounce-delay-ms = <3>; | ||
| nxp,scan-delay-ms = <34>; | ||
| linux,keymap = <0x00000002>; | ||
| status = "okay"; | ||
| }; | ||
|
|
||
| &mac { | ||
| phy-mode = "rmii"; | ||
| use-iram; | ||
| }; | ||
|
|
||
| /* Here, choose exactly one from: ohci, usbd */ | ||
| &ohci /* &usbd */ { | ||
| transceiver = <&isp1301>; | ||
| status = "okay"; | ||
| }; | ||
|
|
||
| &sd { | ||
| wp-gpios = <&gpio 3 0 0>; | ||
| cd-gpios = <&gpio 3 1 0>; | ||
| cd-inverted; | ||
| bus-width = <4>; | ||
| vmmc-supply = <&sd_reg>; | ||
| status = "okay"; | ||
| }; | ||
|
|
||
| /* 64MB Flash via SLC NAND controller */ | ||
| &slc { | ||
| status = "okay"; | ||
|
|
||
| nxp,wdr-clks = <14>; | ||
| nxp,wwidth = <40000000>; | ||
| nxp,whold = <100000000>; | ||
| nxp,wsetup = <100000000>; | ||
| nxp,rdr-clks = <14>; | ||
| nxp,rwidth = <40000000>; | ||
| nxp,rhold = <66666666>; | ||
| nxp,rsetup = <100000000>; | ||
| nand-on-flash-bbt; | ||
| gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ | ||
|
|
||
| partitions { | ||
| compatible = "fixed-partitions"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
|
|
||
| mtd0@00000000 { | ||
| label = "phy3250-boot"; | ||
| reg = <0x00000000 0x00064000>; | ||
| read-only; | ||
| }; | ||
|
|
||
| mtd1@00064000 { | ||
| label = "phy3250-uboot"; | ||
| reg = <0x00064000 0x00190000>; | ||
| read-only; | ||
| }; | ||
|
|
||
| mtd2@001f4000 { | ||
| label = "phy3250-ubt-prms"; | ||
| reg = <0x001f4000 0x00010000>; | ||
| }; | ||
|
|
||
| mtd3@00204000 { | ||
| label = "phy3250-kernel"; | ||
| reg = <0x00204000 0x00400000>; | ||
| }; | ||
|
|
||
| mtd4@00604000 { | ||
| label = "phy3250-rootfs"; | ||
| reg = <0x00604000 0x039fc000>; | ||
| }; | ||
| }; | ||
| }; | ||
|
|
||
| &ssp0 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| num-cs = <1>; | ||
| cs-gpios = <&gpio 3 5 0>; | ||
| status = "okay"; | ||
|
|
||
| eeprom: at25@0 { | ||
| compatible = "atmel,at25"; | ||
| reg = <0>; | ||
| spi-max-frequency = <5000000>; | ||
|
|
||
| pl022,interface = <0>; | ||
| pl022,com-mode = <0>; | ||
| pl022,rx-level-trig = <1>; | ||
| pl022,tx-level-trig = <1>; | ||
| pl022,ctrl-len = <11>; | ||
| pl022,wait-state = <0>; | ||
| pl022,duplex = <0>; | ||
|
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||
| at25,byte-len = <0x8000>; | ||
| at25,addr-mode = <2>; | ||
| at25,page-size = <64>; | ||
| }; | ||
| }; | ||
|
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||
| &tsc { | ||
| status = "okay"; | ||
| }; | ||
|
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||
| &uart2 { | ||
| status = "okay"; | ||
| }; | ||
|
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||
| &uart3 { | ||
| status = "okay"; | ||
| }; | ||
|
|
||
| &uart5 { | ||
| status = "okay"; | ||
| }; |
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