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Merge tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32…
…xx into next/dt Merge "NXP LPC32xx device tree updates for v4.7" from Vladimir Zapolskiy: This includes a few functional changes: * new representation of MIC, SIC1 and SIC2 interrupt controllers, * disabled by default SPI1, SPI2, SSP0 and SSP1 SPI controllers in shared lpc32xx.dtsi file, * added clock sources for SPI1 and SPI2, * set default clock rate of HCLK PLL to main osc rate multiplied by 16. Also there are some non-functional changes: * flatten board DTS files by exploiting device node labels, * add 'partitions' device node for NAND SLC / MTD OF, * correct Atmel vendor prefix to describe on board AT24 EEPROMs, * rename board DTS files by adding SoC name prefix. Since now DTS files of LPC32xx boards match "^lpc32[2345]0-" pattern. * tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx: ARM: dts: lpc32xx: phy3250: add SoC name prefix to board dts file ARM: dts: lpc32xx: phy3250: add NAND partitions device node ARM: dts: lpc32xx: phy3250: avoid extension of device nodes by absolute path ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file ARM: dts: lpc32xx: ea3250: fix Atmel at24 eeprom vendor ARM: dts: lpc32xx: ea3250: add NAND partitions device node ARM: dts: lpc32xx: ea3250: avoid extension of device nodes by absolute path ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC dt-bindings: interrupt-controllers: add description of SIC1 and SIC2 ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default ARM: dts: phy3250: enable ssp0 ARM: dts: lpc32xx: add clock properties to spi nodes ARM: dts: lpc32xx: set default clock rate of HCLK PLL
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Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,38 +1,60 @@ | ||
| * NXP LPC32xx Main Interrupt Controller | ||
| (MIC, including SIC1 and SIC2 secondary controllers) | ||
| * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "nxp,lpc3220-mic" | ||
| - interrupt-controller: Identifies the node as an interrupt controller. | ||
| - interrupt-parent: Empty for the interrupt controller itself | ||
| - #interrupt-cells: The number of cells to define the interrupts. Should be 2. | ||
| The first cell is the IRQ number | ||
| The second cell is used to specify mode: | ||
| 1 = low-to-high edge triggered | ||
| 2 = high-to-low edge triggered | ||
| 4 = active high level-sensitive | ||
| 8 = active low level-sensitive | ||
| Default for internal sources should be set to 4 (active high). | ||
| - reg: Should contain MIC registers location and length | ||
| - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". | ||
| - reg: should contain IC registers location and length. | ||
| - interrupt-controller: identifies the node as an interrupt controller. | ||
| - #interrupt-cells: the number of cells to define an interrupt, should be 2. | ||
| The first cell is the IRQ number, the second cell is used to specify | ||
| one of the supported IRQ types: | ||
| IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, | ||
| IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, | ||
| IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, | ||
| IRQ_TYPE_LEVEL_LOW = active low level-sensitive. | ||
| Reset value is IRQ_TYPE_LEVEL_LOW. | ||
|
|
||
| Optional properties: | ||
| - interrupt-parent: empty for MIC interrupt controller, link to parent | ||
| MIC interrupt controller for SIC1 and SIC2 | ||
| - interrupts: empty for MIC interrupt controller, cascaded MIC | ||
| hardware interrupts for SIC1 and SIC2 | ||
|
|
||
| Examples: | ||
| /* | ||
| * MIC | ||
| */ | ||
|
|
||
| /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ | ||
| mic: interrupt-controller@40008000 { | ||
| compatible = "nxp,lpc3220-mic"; | ||
| reg = <0x40008000 0x4000>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <2>; | ||
| }; | ||
|
|
||
| sic1: interrupt-controller@4000c000 { | ||
| compatible = "nxp,lpc3220-sic"; | ||
| reg = <0x4000c000 0x4000>; | ||
| interrupt-controller; | ||
| interrupt-parent; | ||
| #interrupt-cells = <2>; | ||
| reg = <0x40008000 0xC000>; | ||
|
|
||
| interrupt-parent = <&mic>; | ||
| interrupts = <0 IRQ_TYPE_LEVEL_LOW>, | ||
| <30 IRQ_TYPE_LEVEL_LOW>; | ||
| }; | ||
|
|
||
| /* | ||
| * ADC | ||
| */ | ||
| sic2: interrupt-controller@40010000 { | ||
| compatible = "nxp,lpc3220-sic"; | ||
| reg = <0x40010000 0x4000>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <2>; | ||
|
|
||
| interrupt-parent = <&mic>; | ||
| interrupts = <1 IRQ_TYPE_LEVEL_LOW>, | ||
| <31 IRQ_TYPE_LEVEL_LOW>; | ||
| }; | ||
|
|
||
| /* ADC */ | ||
| adc@40048000 { | ||
| compatible = "nxp,lpc3220-adc"; | ||
| reg = <0x40048000 0x1000>; | ||
| interrupt-parent = <&mic>; | ||
| interrupts = <39 4>; | ||
| interrupt-parent = <&sic1>; | ||
| interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; | ||
| }; |
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