Skip to content

Commit

Permalink
drm/amd/display: num of sw i2c/aux engines less than num of connectors
Browse files Browse the repository at this point in the history 
[why]
AMD Stoney reference board, there are only 2 pipes (not include
underlay), and 3 connectors. resource creation, only
2 I2C/AUX engines are created. Within dc_link_aux_transfer, when
pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL.
NULL point is referred later causing system crash.

[how]
each asic design has fixed number of ddc engines at hw side.
for each ddc engine, create its i2x/aux engine at sw side.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
  • Loading branch information
Hersen Wu authored and Alex Deucher committed Sep 11, 2018
1 parent 86a2da7 commit 0e8e4fb
Show file tree
Hide file tree
Showing 7 changed files with 52 additions and 5 deletions.
6 changes: 5 additions & 1 deletion drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -372,7 +372,8 @@ static const struct resource_caps res_cap = {
.num_timing_generator = 6,
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 3
.num_pll = 3,
.num_ddc = 6,
};

#define CTX ctx
Expand Down Expand Up @@ -1004,6 +1005,9 @@ static bool construct(
"DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand Down
4 changes: 4 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -378,6 +378,7 @@ static const struct resource_caps carrizo_resource_cap = {
.num_audio = 3,
.num_stream_encoder = 3,
.num_pll = 2,
.num_ddc = 3,
};

static const struct resource_caps stoney_resource_cap = {
Expand All @@ -386,6 +387,7 @@ static const struct resource_caps stoney_resource_cap = {
.num_audio = 3,
.num_stream_encoder = 3,
.num_pll = 2,
.num_ddc = 3,
};

#define CTX ctx
Expand Down Expand Up @@ -1336,7 +1338,9 @@ static bool construct(
"DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand Down
5 changes: 5 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -384,13 +384,15 @@ static const struct resource_caps polaris_10_resource_cap = {
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
.num_ddc = 6,
};

static const struct resource_caps polaris_11_resource_cap = {
.num_timing_generator = 5,
.num_audio = 5,
.num_stream_encoder = 5,
.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
.num_ddc = 5,
};

#define CTX ctx
Expand Down Expand Up @@ -1286,6 +1288,9 @@ static bool construct(
"DC:failed to create output pixel processor!\n");
goto res_create_fail;
}
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand Down
9 changes: 7 additions & 2 deletions drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -436,6 +436,7 @@ static const struct resource_caps res_cap = {
.num_audio = 7,
.num_stream_encoder = 6,
.num_pll = 6,
.num_ddc = 6,
};

static const struct dc_debug_options debug_defaults = {
Expand Down Expand Up @@ -1062,6 +1063,12 @@ static bool construct(
dm_error(
"DC: failed to create output pixel processor!\n");
}

/* check next valid pipe */
j++;
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand All @@ -1077,8 +1084,6 @@ static bool construct(
goto res_create_fail;
}
pool->base.sw_i2cs[i] = NULL;
/* check next valid pipe */
j++;
}

/* valid pipe num */
Expand Down
25 changes: 25 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -367,20 +367,23 @@ static const struct resource_caps res_cap = {
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 3,
.num_ddc = 6,
};

static const struct resource_caps res_cap_81 = {
.num_timing_generator = 4,
.num_audio = 7,
.num_stream_encoder = 7,
.num_pll = 3,
.num_ddc = 6,
};

static const struct resource_caps res_cap_83 = {
.num_timing_generator = 2,
.num_audio = 6,
.num_stream_encoder = 6,
.num_pll = 2,
.num_ddc = 2,
};

static const struct dce_dmcu_registers dmcu_regs = {
Expand Down Expand Up @@ -992,7 +995,9 @@ static bool dce80_construct(
dm_error("DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand Down Expand Up @@ -1200,6 +1205,16 @@ static bool dce81_construct(
dm_error("DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC:failed to create aux engine!!\n");
goto res_create_fail;
}
pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
if (pool->base.hw_i2cs[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand Down Expand Up @@ -1396,6 +1411,16 @@ static bool dce83_construct(
dm_error("DC: failed to create output pixel processor!\n");
goto res_create_fail;
}
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error(
"DC:failed to create aux engine!!\n");
goto res_create_fail;
}
pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
if (pool->base.hw_i2cs[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand Down
7 changes: 5 additions & 2 deletions drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -501,6 +501,7 @@ static const struct resource_caps res_cap = {
.num_audio = 4,
.num_stream_encoder = 4,
.num_pll = 4,
.num_ddc = 4,
};

static const struct dc_debug_options debug_defaults_drv = {
Expand Down Expand Up @@ -1334,7 +1335,11 @@ static bool construct(
dm_error("DC: failed to create tg!\n");
goto fail;
}
/* check next valid pipe */
j++;
}

for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
Expand All @@ -1350,8 +1355,6 @@ static bool construct(
goto fail;
}
pool->base.sw_i2cs[i] = NULL;
/* check next valid pipe */
j++;
}

/* valid pipe num */
Expand Down
1 change: 1 addition & 0 deletions drivers/gpu/drm/amd/display/dc/inc/resource.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@ struct resource_caps {
int num_stream_encoder;
int num_pll;
int num_dwb;
int num_ddc;
};

struct resource_straps {
Expand Down

0 comments on commit 0e8e4fb

Please sign in to comment.