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RISC-V: Initial DTS for Microchip ICICLE board
Add initial DTS for Microchip ICICLE board having only essential devices (clocks, sdhci, ethernet, serial, etc). The device tree is based on the U-Boot patch. https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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Atish Patra
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Palmer Dabbelt
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Apr 26, 2021
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# SPDX-License-Identifier: GPL-2.0 | ||
subdir-y += sifive | ||
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan | ||
subdir-y += microchip | ||
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obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) |
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# SPDX-License-Identifier: GPL-2.0 | ||
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb |
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arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT) | ||
/* Copyright (c) 2020 Microchip Technology Inc */ | ||
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/dts-v1/; | ||
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#include "microchip-mpfs.dtsi" | ||
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/* Clock frequency (in Hz) of the rtcclk */ | ||
#define RTCCLK_FREQ 1000000 | ||
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/ { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
model = "Microchip PolarFire-SoC Icicle Kit"; | ||
compatible = "microchip,mpfs-icicle-kit"; | ||
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chosen { | ||
stdout-path = &serial0; | ||
}; | ||
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cpus { | ||
timebase-frequency = <RTCCLK_FREQ>; | ||
}; | ||
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memory@80000000 { | ||
device_type = "memory"; | ||
reg = <0x0 0x80000000 0x0 0x40000000>; | ||
clocks = <&clkcfg 26>; | ||
}; | ||
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soc { | ||
}; | ||
}; | ||
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&serial0 { | ||
status = "okay"; | ||
}; | ||
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&serial1 { | ||
status = "okay"; | ||
}; | ||
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&serial2 { | ||
status = "okay"; | ||
}; | ||
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&serial3 { | ||
status = "okay"; | ||
}; | ||
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&sdcard { | ||
status = "okay"; | ||
}; | ||
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&emac0 { | ||
phy-mode = "sgmii"; | ||
phy-handle = <&phy0>; | ||
phy0: ethernet-phy@8 { | ||
reg = <8>; | ||
ti,fifo-depth = <0x01>; | ||
}; | ||
}; | ||
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&emac1 { | ||
status = "okay"; | ||
phy-mode = "sgmii"; | ||
phy-handle = <&phy1>; | ||
phy1: ethernet-phy@9 { | ||
reg = <9>; | ||
ti,fifo-depth = <0x01>; | ||
}; | ||
}; |
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