Skip to content

Commit

Permalink
RISC-V: Initial DTS for Microchip ICICLE board
Browse files Browse the repository at this point in the history
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.

https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
  • Loading branch information
Atish Patra authored and Palmer Dabbelt committed Apr 26, 2021
1 parent d53b024 commit 0fa6107
Showing 4 changed files with 404 additions and 0 deletions.
1 change: 1 addition & 0 deletions arch/riscv/boot/dts/Makefile
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip

obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
2 changes: 2 additions & 0 deletions arch/riscv/boot/dts/microchip/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
72 changes: 72 additions & 0 deletions arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020 Microchip Technology Inc */

/dts-v1/;

#include "microchip-mpfs.dtsi"

/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000

/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-kit";

chosen {
stdout-path = &serial0;
};

cpus {
timebase-frequency = <RTCCLK_FREQ>;
};

memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
clocks = <&clkcfg 26>;
};

soc {
};
};

&serial0 {
status = "okay";
};

&serial1 {
status = "okay";
};

&serial2 {
status = "okay";
};

&serial3 {
status = "okay";
};

&sdcard {
status = "okay";
};

&emac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
phy0: ethernet-phy@8 {
reg = <8>;
ti,fifo-depth = <0x01>;
};
};

&emac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
ti,fifo-depth = <0x01>;
};
};
Loading

0 comments on commit 0fa6107

Please sign in to comment.