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RDMA/hns: Refactor hns_roce_create_srq()
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Split the SRQ creation process into multiple steps and encapsulate them
into functions.

Link: https://lore.kernel.org/r/1611997090-48820-7-git-send-email-liweihang@huawei.com
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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Wenpeng Liang authored and Jason Gunthorpe committed Feb 8, 2021
1 parent 6ee00fb commit 0fee451
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Showing 3 changed files with 161 additions and 125 deletions.
5 changes: 3 additions & 2 deletions drivers/infiniband/hw/hns/hns_roce_device.h
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Original file line number Diff line number Diff line change
Expand Up @@ -506,6 +506,7 @@ struct hns_roce_srq {
int max_gs;
u32 rsv_sge;
int wqe_shift;
u32 cqn;
void __iomem *db_reg_l;

atomic_t refcount;
Expand Down Expand Up @@ -953,8 +954,8 @@ struct hns_roce_hw {
int (*init_eq)(struct hns_roce_dev *hr_dev);
void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
void (*write_srqc)(struct hns_roce_dev *hr_dev,
struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
struct hns_roce_srq *srq, void *mb_buf,
u64 *mtts_wqe, u64 *mtts_idx,
dma_addr_t dma_handle_wqe,
dma_addr_t dma_handle_idx);
int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
Expand Down
12 changes: 6 additions & 6 deletions drivers/infiniband/hw/hns/hns_roce_hw_v2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5228,9 +5228,9 @@ static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
}

static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
u32 cqn, void *mb_buf, u64 *mtts_wqe,
u64 *mtts_idx, dma_addr_t dma_handle_wqe,
struct hns_roce_srq *srq, void *mb_buf,
u64 *mtts_wqe, u64 *mtts_idx,
dma_addr_t dma_handle_wqe,
dma_addr_t dma_handle_idx)
{
struct hns_roce_srq_context *srq_context;
Expand All @@ -5257,7 +5257,7 @@ static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);

roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
SRQC_BYTE_12_SRQ_XRCD_S, 0);

srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));

Expand All @@ -5267,7 +5267,7 @@ static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
dma_handle_wqe >> 35);

roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
SRQC_BYTE_28_PD_S, pdn);
SRQC_BYTE_28_PD_S, to_hr_pd(srq->ibsrq.pd)->pdn);
roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
fls(srq->max_gs - 1));
Expand Down Expand Up @@ -5307,7 +5307,7 @@ static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
roce_set_field(srq_context->byte_56_xrc_cqn,
SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
cqn);
srq->cqn);
roce_set_field(srq_context->byte_56_xrc_cqn,
SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
Expand Down
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