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[SCSI] isci: fix sgpio register definitions
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output_data_select registers are off by one u32

delete the macros we will never use.

Reported-by: Artur Wojcik <artur.wojcik@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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Dan Williams authored and James Bottomley committed Sep 22, 2011
1 parent 8ec6552 commit 13257cf
Showing 1 changed file with 4 additions and 118 deletions.
122 changes: 4 additions & 118 deletions drivers/scsi/isci/registers.h
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Original file line number Diff line number Diff line change
Expand Up @@ -875,122 +875,6 @@ struct scu_iit_entry {
#define SCU_PTSxSR_GEN_BIT(name) \
SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name)


/*
* *****************************************************************************
* * SGPIO Register shift and mask values
* ***************************************************************************** */
#define SCU_SGPIO_CONTROL_SGPIO_ENABLE_SHIFT (0)
#define SCU_SGPIO_CONTROL_SGPIO_ENABLE_MASK (0x00000001)
#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_SHIFT (1)
#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_MASK (0x00000002)
#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_SHIFT (2)
#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_MASK (0x00000004)
#define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_SHIFT (15)
#define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_MASK (0x00008000)
#define SCU_SGPIO_CONTROL_SGPIO_RESERVED_MASK (0xFFFF7FF8)

#define SCU_SGICRx_GEN_BIT(name) \
SCU_GEN_BIT(SCU_SGPIO_CONTROL_SGPIO_ ## name)

#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_SHIFT (0)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_MASK (0x0000000F)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_SHIFT (4)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_MASK (0x000000F0)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_SHIFT (8)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_MASK (0x00000F00)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_SHIFT (12)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_MASK (0x0000F000)
#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_RESERVED_MASK (0xFFFF0000)

#define SCU_SGPBRx_GEN_VAL(name, value) \
SCU_GEN_VALUE(SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_ ## name, value)

#define SCU_SGPIO_START_DRIVE_LOWER_R0_SHIFT (0)
#define SCU_SGPIO_START_DRIVE_LOWER_R0_MASK (0x00000003)
#define SCU_SGPIO_START_DRIVE_LOWER_R1_SHIFT (4)
#define SCU_SGPIO_START_DRIVE_LOWER_R1_MASK (0x00000030)
#define SCU_SGPIO_START_DRIVE_LOWER_R2_SHIFT (8)
#define SCU_SGPIO_START_DRIVE_LOWER_R2_MASK (0x00000300)
#define SCU_SGPIO_START_DRIVE_LOWER_R3_SHIFT (12)
#define SCU_SGPIO_START_DRIVE_LOWER_R3_MASK (0x00003000)
#define SCU_SGPIO_START_DRIVE_LOWER_RESERVED_MASK (0xFFFF8888)

#define SCU_SGSDLRx_GEN_VAL(name, value) \
SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value)

#define SCU_SGPIO_START_DRIVE_UPPER_R0_SHIFT (0)
#define SCU_SGPIO_START_DRIVE_UPPER_R0_MASK (0x00000003)
#define SCU_SGPIO_START_DRIVE_UPPER_R1_SHIFT (4)
#define SCU_SGPIO_START_DRIVE_UPPER_R1_MASK (0x00000030)
#define SCU_SGPIO_START_DRIVE_UPPER_R2_SHIFT (8)
#define SCU_SGPIO_START_DRIVE_UPPER_R2_MASK (0x00000300)
#define SCU_SGPIO_START_DRIVE_UPPER_R3_SHIFT (12)
#define SCU_SGPIO_START_DRIVE_UPPER_R3_MASK (0x00003000)
#define SCU_SGPIO_START_DRIVE_UPPER_RESERVED_MASK (0xFFFF8888)

#define SCU_SGSDURx_GEN_VAL(name, value) \
SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value)

#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_SHIFT (0)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_MASK (0x00000003)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_SHIFT (4)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_MASK (0x00000030)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_SHIFT (8)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_MASK (0x00000300)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_SHIFT (12)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_MASK (0x00003000)
#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_RESERVED_MASK (0xFFFF8888)

#define SCU_SGSIDLRx_GEN_VAL(name, value) \
SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value)

#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_SHIFT (0)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_MASK (0x00000003)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_SHIFT (4)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_MASK (0x00000030)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_SHIFT (8)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_MASK (0x00000300)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_SHIFT (12)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_MASK (0x00003000)
#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_RESERVED_MASK (0xFFFF8888)

#define SCU_SGSIDURx_GEN_VAL(name, value) \
SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value)

#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_SHIFT (0)
#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_MASK (0x0000000F)
#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_RESERVED_MASK (0xFFFFFFF0)

#define SCU_SGVSCR_GEN_VAL(value) \
SCU_GEN_VALUE(SCU_SGPIO_VENDOR_SPECIFIC_CODE ## name, value)

#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_SHIFT (0)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_MASK (0x00000003)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_SHIFT (2)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_MASK (0x00000004)
#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_SHIFT (3)
#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_MASK (0x00000008)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_SHIFT (4)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_MASK (0x00000030)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_SHIFT (6)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_MASK (0x00000040)
#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_SHIFT (7)
#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_MASK (0x00000080)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_SHIFT (8)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_MASK (0x00000300)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_SHIFT (10)
#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_MASK (0x00000400)
#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_SHIFT (11)
#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_MASK (0x00000800)
#define SCU_SGPIO_OUPUT_DATA_SELECT_RESERVED_MASK (0xFFFFF000)

#define SCU_SGODSR_GEN_VAL(name, value) \
SCU_GEN_VALUE(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name, value)

#define SCU_SGODSR_GEN_BIT(name) \
SCU_GEN_BIT(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name)

/*
* *****************************************************************************
* * SMU Registers
Expand Down Expand Up @@ -1529,10 +1413,12 @@ struct scu_sgpio_registers {
u32 serial_input_upper;
/* 0x0018 SGPIO_SGVSCR */
u32 vendor_specific_code;
/* 0x001C Reserved */
u32 reserved_001c;
/* 0x0020 SGPIO_SGODSR */
u32 ouput_data_select[8];
u32 output_data_select[8];
/* Remainder of memory space 256 bytes */
u32 reserved_1444_14ff[0x31];
u32 reserved_1444_14ff[0x30];

};

Expand Down

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