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Merge tag 'dmaengine-5.12-rc1' of git://git.kernel.org/pub/scm/linux/…
…kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "We have couple of drivers removed a new driver and bunch of new device support and few updates to drivers for this round. New drivers/devices: - Intel LGM SoC DMA driver - Actions Semi S500 DMA controller - Renesas r8a779a0 dma controller - Ingenic JZ4760(B) dma controller - Intel KeemBay AxiDMA controller Removed: - Coh901318 dma driver - Zte zx dma driver - Sirfsoc dma driver Updates: - mmp_pdma, mmp_tdma gained module support - imx-sdma become modern and dropped platform data support - dw-axi driver gained slave and cyclic dma support" * tag 'dmaengine-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (58 commits) dmaengine: dw-axi-dmac: remove redundant null check on desc dmaengine: xilinx_dma: Alloc tx descriptors GFP_NOWAIT dmaengine: dw-axi-dmac: Virtually split the linked-list dmaengine: dw-axi-dmac: Set constraint to the Max segment size dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support dmaengine: drivers: Kconfig: add HAS_IOMEM dependency to DW_AXI_DMAC dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA dmaengine: dw-axi-dmac: Support burst residue granularity dmaengine: dw-axi-dmac: Support of_dma_controller_register() dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() dmaengine: dw-axi-dmac: Support device_prep_slave_sg dmaengine: dw-axi-dmac: Add device_config operation dmaengine: dw-axi-dmac: Add device_synchronize() callback dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() dmaengine: dw-axi-dmac: simplify descriptor management dt-bindings: dma: Add YAML schemas for dw-axi-dmac dmaengine: ti: k3-psil: optimize struct psil_endpoint_config for size ...
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,116 @@ | ||
| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/dma/intel,ldma.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: Lightning Mountain centralized DMA controllers. | ||
|
|
||
| maintainers: | ||
| - chuanhua.lei@intel.com | ||
| - mallikarjunax.reddy@intel.com | ||
|
|
||
| allOf: | ||
| - $ref: "dma-controller.yaml#" | ||
|
|
||
| properties: | ||
| compatible: | ||
| enum: | ||
| - intel,lgm-cdma | ||
| - intel,lgm-dma2tx | ||
| - intel,lgm-dma1rx | ||
| - intel,lgm-dma1tx | ||
| - intel,lgm-dma0tx | ||
| - intel,lgm-dma3 | ||
| - intel,lgm-toe-dma30 | ||
| - intel,lgm-toe-dma31 | ||
|
|
||
| reg: | ||
| maxItems: 1 | ||
|
|
||
| "#dma-cells": | ||
| const: 3 | ||
| description: | ||
| The first cell is the peripheral's DMA request line. | ||
| The second cell is the peripheral's (port) number corresponding to the channel. | ||
| The third cell is the burst length of the channel. | ||
|
|
||
| dma-channels: | ||
| minimum: 1 | ||
| maximum: 16 | ||
|
|
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| dma-channel-mask: | ||
| maxItems: 1 | ||
|
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| clocks: | ||
| maxItems: 1 | ||
|
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| resets: | ||
| maxItems: 1 | ||
|
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| reset-names: | ||
| items: | ||
| - const: ctrl | ||
|
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| interrupts: | ||
| maxItems: 1 | ||
|
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| intel,dma-poll-cnt: | ||
| $ref: /schemas/types.yaml#/definitions/uint32 | ||
| description: | ||
| DMA descriptor polling counter is used to control the poling mechanism | ||
| for the descriptor fetching for all channels. | ||
|
|
||
| intel,dma-byte-en: | ||
| type: boolean | ||
| description: | ||
| DMA byte enable is only valid for DMA write(RX). | ||
| Byte enable(1) means DMA write will be based on the number of dwords | ||
| instead of the whole burst. | ||
|
|
||
| intel,dma-drb: | ||
| type: boolean | ||
| description: | ||
| DMA descriptor read back to make sure data and desc synchronization. | ||
|
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||
| intel,dma-dburst-wr: | ||
| type: boolean | ||
| description: | ||
| Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst; | ||
| if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16. | ||
| It only applies to RX DMA and memcopy DMA. | ||
|
|
||
| required: | ||
| - compatible | ||
| - reg | ||
|
|
||
| additionalProperties: false | ||
|
|
||
| examples: | ||
| - | | ||
| dma0: dma-controller@e0e00000 { | ||
| compatible = "intel,lgm-cdma"; | ||
| reg = <0xe0e00000 0x1000>; | ||
| #dma-cells = <3>; | ||
| dma-channels = <16>; | ||
| dma-channel-mask = <0xFFFF>; | ||
| interrupt-parent = <&ioapic1>; | ||
| interrupts = <82 1>; | ||
| resets = <&rcu0 0x30 0>; | ||
| reset-names = "ctrl"; | ||
| clocks = <&cgu0 80>; | ||
| intel,dma-poll-cnt = <4>; | ||
| intel,dma-byte-en; | ||
| intel,dma-drb; | ||
| }; | ||
| - | | ||
| dma3: dma-controller@ec800000 { | ||
| compatible = "intel,lgm-dma3"; | ||
| reg = <0xec800000 0x1000>; | ||
| clocks = <&cgu0 71>; | ||
| resets = <&rcu0 0x10 9>; | ||
| #dma-cells = <3>; | ||
| intel,dma-poll-cnt = <16>; | ||
| intel,dma-byte-en; | ||
| intel,dma-dburst-wr; | ||
| }; |
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Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
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