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Merge tag 'soc-drivers-6.10' of git://git.kernel.org/pub/scm/linux/ke…
…rnel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "As usual, these are updates for drivers that are specific to certain SoCs or firmware running on them. Notable updates include - The new STMicroelectronics STM32 "firewall" bus driver that is used to provide a barrier between different parts of an SoC - Lots of updates for the Qualcomm platform drivers, in particular SCM, which gets a rewrite of its initialization code - Firmware driver updates for Arm FF-A notification interrupts and indirect messaging, SCMI firmware support for pin control and vendor specific interfaces, and TEE firmware interface changes across multiple TEE drivers - A larger cleanup of the Mediatek CMDQ driver and some related bits - Kconfig changes for riscv drivers to prepare for adding Kanaan k230 support - Multiple minor updates for the TI sysc bus driver, memory controllers, hisilicon hccs and more" * tag 'soc-drivers-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (103 commits) firmware: qcom: uefisecapp: Allow on sc8180x Primus and Flex 5G soc: qcom: pmic_glink: Make client-lock non-sleeping dt-bindings: soc: qcom,wcnss: fix bluetooth address example soc/tegra: pmc: Add EQOS wake event for Tegra194 and Tegra234 bus: stm32_firewall: fix off by one in stm32_firewall_get_firewall() bus: etzpc: introduce ETZPC firewall controller driver firmware: arm_ffa: Avoid queuing work when running on the worker queue bus: ti-sysc: Drop legacy idle quirk handling bus: ti-sysc: Drop legacy quirk handling for smartreflex bus: ti-sysc: Drop legacy quirk handling for uarts bus: ti-sysc: Add a description and copyrights bus: ti-sysc: Move check for no-reset-on-init soc: hisilicon: kunpeng_hccs: replace MAILBOX dependency with PCC soc: hisilicon: kunpeng_hccs: Add the check for obtaining complete port attribute firmware: arm_ffa: Fix memory corruption in ffa_msg_send2() bus: rifsc: introduce RIFSC firewall controller driver of: property: fw_devlink: Add support for "access-controller" soc: mediatek: mtk-socinfo: Correct the marketing name for MT8188GV soc: mediatek: mtk-socinfo: Add entry for MT8395AV/ZA Genio 1200 soc: mediatek: mtk-mutex: Add support for MT8188 VPPSYS ...
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Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Generic Domain Access Controllers | ||
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maintainers: | ||
- Oleksii Moisieiev <oleksii_moisieiev@epam.com> | ||
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description: |+ | ||
Common access controllers properties | ||
Access controllers are in charge of stating which of the hardware blocks under | ||
their responsibility (their domain) can be accesssed by which compartment. A | ||
compartment can be a cluster of CPUs (or coprocessors), a range of addresses | ||
or a group of hardware blocks. An access controller's domain is the set of | ||
resources covered by the access controller. | ||
This device tree binding can be used to bind devices to their access | ||
controller provided by access-controllers property. In this case, the device | ||
is a consumer and the access controller is the provider. | ||
An access controller can be represented by any node in the device tree and | ||
can provide one or more configuration parameters, needed to control parameters | ||
of the consumer device. A consumer node can refer to the provider by phandle | ||
and a set of phandle arguments, specified by '#access-controller-cells' | ||
property in the access controller node. | ||
Access controllers are typically used to set/read the permissions of a | ||
hardware block and grant access to it. Any of which depends on the access | ||
controller. The capabilities of each access controller are defined by the | ||
binding of the access controller device. | ||
Each node can be a consumer for the several access controllers. | ||
# always select the core schema | ||
select: true | ||
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properties: | ||
"#access-controller-cells": | ||
description: | ||
Number of cells in an access-controllers specifier; | ||
Can be any value as specified by device tree binding documentation | ||
of a particular provider. The node is an access controller. | ||
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access-controller-names: | ||
$ref: /schemas/types.yaml#/definitions/string-array | ||
description: | ||
A list of access-controllers names, sorted in the same order as | ||
access-controllers entries. Consumer drivers will use | ||
access-controller-names to match with existing access-controllers entries. | ||
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access-controllers: | ||
$ref: /schemas/types.yaml#/definitions/phandle-array | ||
description: | ||
A list of access controller specifiers, as defined by the | ||
bindings of the access-controllers provider. | ||
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additionalProperties: true | ||
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examples: | ||
- | | ||
clock_controller: access-controllers@50000 { | ||
reg = <0x50000 0x400>; | ||
#access-controller-cells = <2>; | ||
}; | ||
bus_controller: bus@60000 { | ||
reg = <0x60000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
ranges; | ||
#access-controller-cells = <3>; | ||
uart4: serial@60100 { | ||
reg = <0x60100 0x400>; | ||
clocks = <&clk_serial>; | ||
access-controllers = <&clock_controller 1 2>, | ||
<&bus_controller 1 3 5>; | ||
access-controller-names = "clock", "bus"; | ||
}; | ||
}; |
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: STM32 Extended TrustZone protection controller | ||
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description: | | ||
The ETZPC configures TrustZone security in a SoC having bus masters and | ||
devices with programmable-security attributes (securable resources). | ||
maintainers: | ||
- Gatien Chevallier <gatien.chevallier@foss.st.com> | ||
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select: | ||
properties: | ||
compatible: | ||
contains: | ||
const: st,stm32-etzpc | ||
required: | ||
- compatible | ||
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properties: | ||
compatible: | ||
items: | ||
- const: st,stm32-etzpc | ||
- const: simple-bus | ||
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reg: | ||
maxItems: 1 | ||
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"#address-cells": | ||
const: 1 | ||
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"#size-cells": | ||
const: 1 | ||
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ranges: true | ||
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"#access-controller-cells": | ||
const: 1 | ||
description: | ||
Contains the firewall ID associated to the peripheral. | ||
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patternProperties: | ||
"^.*@[0-9a-f]+$": | ||
description: Peripherals | ||
type: object | ||
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additionalProperties: true | ||
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required: | ||
- access-controllers | ||
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required: | ||
- compatible | ||
- reg | ||
- "#address-cells" | ||
- "#size-cells" | ||
- "#access-controller-cells" | ||
- ranges | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
// In this example, the usart2 device refers to rifsc as its access | ||
// controller. | ||
// Access rights are verified before creating devices. | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
#include <dt-bindings/clock/stm32mp13-clks.h> | ||
#include <dt-bindings/reset/stm32mp13-resets.h> | ||
etzpc: bus@5c007000 { | ||
compatible = "st,stm32-etzpc", "simple-bus"; | ||
reg = <0x5c007000 0x400>; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
#access-controller-cells = <1>; | ||
ranges; | ||
usart2: serial@4c001000 { | ||
compatible = "st,stm32h7-uart"; | ||
reg = <0x4c001000 0x400>; | ||
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&rcc USART2_K>; | ||
resets = <&rcc USART2_R>; | ||
wakeup-source; | ||
dmas = <&dmamux1 43 0x400 0x5>, | ||
<&dmamux1 44 0x400 0x1>; | ||
dma-names = "rx", "tx"; | ||
access-controllers = <&etzpc 17>; | ||
}; | ||
}; |
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Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: STM32 Resource isolation framework security controller | ||
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maintainers: | ||
- Gatien Chevallier <gatien.chevallier@foss.st.com> | ||
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description: | | ||
Resource isolation framework (RIF) is a comprehensive set of hardware blocks | ||
designed to enforce and manage isolation of STM32 hardware resources like | ||
memory and peripherals. | ||
The RIFSC (RIF security controller) is composed of three sets of registers, | ||
each managing a specific set of hardware resources: | ||
- RISC registers associated with RISUP logic (resource isolation device unit | ||
for peripherals), assign all non-RIF aware peripherals to zero, one or | ||
any security domains (secure, privilege, compartment). | ||
- RIMC registers: associated with RIMU logic (resource isolation master | ||
unit), assign all non RIF-aware bus master to one security domain by | ||
setting secure, privileged and compartment information on the system bus. | ||
Alternatively, the RISUP logic controlling the device port access to a | ||
peripheral can assign target bus attributes to this peripheral master port | ||
(supported attribute: CID). | ||
- RISC registers associated with RISAL logic (resource isolation device unit | ||
for address space - Lite version), assign address space subregions to one | ||
security domains (secure, privilege, compartment). | ||
select: | ||
properties: | ||
compatible: | ||
contains: | ||
const: st,stm32mp25-rifsc | ||
required: | ||
- compatible | ||
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properties: | ||
compatible: | ||
items: | ||
- const: st,stm32mp25-rifsc | ||
- const: simple-bus | ||
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reg: | ||
maxItems: 1 | ||
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"#address-cells": | ||
const: 1 | ||
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"#size-cells": | ||
const: 1 | ||
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ranges: true | ||
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"#access-controller-cells": | ||
const: 1 | ||
description: | ||
Contains the firewall ID associated to the peripheral. | ||
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patternProperties: | ||
"^.*@[0-9a-f]+$": | ||
description: Peripherals | ||
type: object | ||
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additionalProperties: true | ||
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required: | ||
- access-controllers | ||
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required: | ||
- compatible | ||
- reg | ||
- "#address-cells" | ||
- "#size-cells" | ||
- "#access-controller-cells" | ||
- ranges | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
// In this example, the usart2 device refers to rifsc as its domain | ||
// controller. | ||
// Access rights are verified before creating devices. | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
rifsc: bus@42080000 { | ||
compatible = "st,stm32mp25-rifsc", "simple-bus"; | ||
reg = <0x42080000 0x1000>; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
#access-controller-cells = <1>; | ||
ranges; | ||
usart2: serial@400e0000 { | ||
compatible = "st,stm32h7-uart"; | ||
reg = <0x400e0000 0x400>; | ||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&ck_flexgen_08>; | ||
access-controllers = <&rifsc 32>; | ||
}; | ||
}; |
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