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Merge tag 'drm-misc-next-2019-04-04' of git://anongit.freedesktop.org…
…/drm/drm-misc into drm-next drm-misc-next for 5.2: UAPI Changes: -syncobj: Add TIMELINE_WAIT|QUERY|TRANSFER|TIMELINE_SIGNAL ioctls (Chunming) -Clarify that 1.0 can be represented by drm_color_lut (Daniel) Cross-subsystem Changes: -dt-bindings: Add binding for rk3066 hdmi (Johan) -dt-bindings: Add binding for Feiyang FY07024DI26A30-D panel (Jagan) -dt-bindings: Add Rocktech vendor prefix and jh057n00900 panel bindings (Guido) -MAINTAINERS: Add lima and ASPEED entries (Joel & Qiang) Core Changes: -memory: use dma_alloc_coherent when mem encryption is active (Christian) -dma_buf: add support for a dma_fence chain (Christian) -shmem_gem: fix off-by-one bug in new shmem gem helpers (Dan) Driver Changes: -rockchip: Add support for rk3066 hdmi (Johan) -ASPEED: Add driver supporting ASPEED BMC display controller to drm (Joel) -lima: Add driver supporting Arm Mali4xx gpus to drm (Qiang) -vc4/v3d: Various cleanups and improved error handling (Eric) -panel: Add support for Feiyang FY07024DI26A30-D MIPI-DSI panel (Jagan) -panel: Add support for Rocktech jh057n00900 MIPI-DSI panel (Guido) Cc: Johan Jonker <jbx6244@gmail.com> Cc: Christian König <christian.koenig@amd.com> Cc: Chunming Zhou <david1.zhou@amd.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: Eric Anholt <eric@anholt.net> Cc: Qiang Yu <yuq825@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Guido Günther <agx@sigxcpu.org> Cc: Joel Stanley <joel@jms.id.au> [airlied: fixed XA limit build breakage, Rodrigo also submitted the same patch, but I squashed it in the merge.] Signed-off-by: Dave Airlie <airlied@redhat.com> From: Sean Paul <sean@poorly.run> Link: https://patchwork.freedesktop.org/patch/msgid/20190404201016.GA139524@art_vandelay
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Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.txt
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Feiyang FY07024DI26A30-D 7" MIPI-DSI LCD Panel | ||
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Required properties: | ||
- compatible: must be "feiyang,fy07024di26a30d" | ||
- reg: DSI virtual channel used by that screen | ||
- avdd-supply: analog regulator dc1 switch | ||
- dvdd-supply: 3v3 digital regulator | ||
- reset-gpios: a GPIO phandle for the reset pin | ||
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Optional properties: | ||
- backlight: phandle for the backlight control. | ||
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panel@0 { | ||
compatible = "feiyang,fy07024di26a30d"; | ||
reg = <0>; | ||
avdd-supply = <®_dc1sw>; | ||
dvdd-supply = <®_dldo2>; | ||
reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ | ||
backlight = <&backlight>; | ||
}; |
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Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt
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Rocktech jh057n00900 5.5" 720x1440 TFT LCD panel | ||
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Required properties: | ||
- compatible: should be "rocktech,jh057n00900" | ||
- reg: DSI virtual channel of the peripheral | ||
- reset-gpios: panel reset gpio | ||
- backlight: phandle of the backlight device attached to the panel | ||
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Example: | ||
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&mipi_dsi { | ||
panel@0 { | ||
compatible = "rocktech,jh057n00900"; | ||
reg = <0>; | ||
backlight = <&backlight>; | ||
reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; | ||
}; | ||
}; |
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Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.txt
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Rockchip specific extensions for rk3066 HDMI | ||
============================================ | ||
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Required properties: | ||
- compatible: | ||
"rockchip,rk3066-hdmi"; | ||
- reg: | ||
Physical base address and length of the controller's registers. | ||
- clocks, clock-names: | ||
Phandle to HDMI controller clock, name should be "hclk". | ||
- interrupts: | ||
HDMI interrupt number. | ||
- power-domains: | ||
Phandle to the RK3066_PD_VIO power domain. | ||
- rockchip,grf: | ||
This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1. | ||
- ports: | ||
Contains one port node with two endpoints, numbered 0 and 1, | ||
connected respectively to vop0 and vop1. | ||
Contains one port node with one endpoint | ||
connected to a hdmi-connector node. | ||
- pinctrl-0, pinctrl-name: | ||
Switch the iomux for the HPD/I2C pins to HDMI function. | ||
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Example: | ||
hdmi: hdmi@10116000 { | ||
compatible = "rockchip,rk3066-hdmi"; | ||
reg = <0x10116000 0x2000>; | ||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&cru HCLK_HDMI>; | ||
clock-names = "hclk"; | ||
power-domains = <&power RK3066_PD_VIO>; | ||
rockchip,grf = <&grf>; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; | ||
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ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
hdmi_in: port@0 { | ||
reg = <0>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
hdmi_in_vop0: endpoint@0 { | ||
reg = <0>; | ||
remote-endpoint = <&vop0_out_hdmi>; | ||
}; | ||
hdmi_in_vop1: endpoint@1 { | ||
reg = <1>; | ||
remote-endpoint = <&vop1_out_hdmi>; | ||
}; | ||
}; | ||
hdmi_out: port@1 { | ||
reg = <1>; | ||
hdmi_out_con: endpoint { | ||
remote-endpoint = <&hdmi_con_in>; | ||
}; | ||
}; | ||
}; | ||
}; | ||
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&pinctrl { | ||
hdmi { | ||
hdmi_hpd: hdmi-hpd { | ||
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; | ||
}; | ||
hdmii2c_xfer: hdmii2c-xfer { | ||
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, | ||
<0 RK_PA2 1 &pcfg_pull_none>; | ||
}; | ||
}; | ||
}; |
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Device tree configuration for the GFX display device on the ASPEED SoCs | ||
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Required properties: | ||
- compatible | ||
* Must be one of the following: | ||
+ aspeed,ast2500-gfx | ||
+ aspeed,ast2400-gfx | ||
* In addition, the ASPEED pinctrl bindings require the 'syscon' property to | ||
be present | ||
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- reg: Physical base address and length of the GFX registers | ||
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- interrupts: interrupt number for the GFX device | ||
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- clocks: clock number used to generate the pixel clock | ||
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- resets: reset line that must be released to use the GFX device | ||
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- memory-region: | ||
Phandle to a memory region to allocate from, as defined in | ||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt | ||
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Example: | ||
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gfx: display@1e6e6000 { | ||
compatible = "aspeed,ast2500-gfx", "syscon"; | ||
reg = <0x1e6e6000 0x1000>; | ||
reg-io-width = <4>; | ||
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; | ||
resets = <&syscon ASPEED_RESET_CRT1>; | ||
interrupts = <0x19>; | ||
memory-region = <&gfx_memory>; | ||
}; | ||
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gfx_memory: framebuffer { | ||
size = <0x01000000>; | ||
alignment = <0x01000000>; | ||
compatible = "shared-dma-pool"; | ||
reusable; | ||
}; |
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obj-y := dma-buf.o dma-fence.o dma-fence-array.o reservation.o seqno-fence.o | ||
obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \ | ||
reservation.o seqno-fence.o | ||
obj-$(CONFIG_SYNC_FILE) += sync_file.o | ||
obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o | ||
obj-$(CONFIG_UDMABUF) += udmabuf.o |
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