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MIPS: SEAD3: Disable L2 cache on SEAD-3.
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The cores used on the SEAD-3 platform do not have L2 caches, so
this option should not be turned on. Originally fixed on public
'linux-mti-3.8' release branch.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5559/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Steven J. Hill authored and Ralf Baechle committed Jul 1, 2013
1 parent 7ac836c commit 1535ac0
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1 change: 0 additions & 1 deletion arch/mips/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -342,7 +342,6 @@ config MIPS_SEAD3
select DMA_NONCOHERENT
select IRQ_CPU
select IRQ_GIC
select MIPS_CPU_SCACHE
select MIPS_MSC
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
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