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clk: spear3xx: Use proper control register offset
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The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a6 (SPEAr: Switch to common clock framework).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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Thomas Gleixner authored and Mike Turquette committed Jul 13, 2014
1 parent c556bcd commit 15ebb05
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion drivers/clk/spear/spear3xx_clock.c
Original file line number Diff line number Diff line change
Expand Up @@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { }
/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320

#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010)
#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)

#define SPEAR320_UARTX_PCLK_MASK 0x1
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