MIPS: Octeon: Support 256 MSI on PCIe

Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
mariux64 · Aug 5, 2010 · 1aa2b27 · 1aa2b27
1 parent 0c2f455
commit 1aa2b27
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Showing 2 changed files with 178 additions and 118 deletions.
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,7 +172,7 @@
 #ifdef CONFIG_PCI_MSI
 /* 152 - 215 represent the MSI interrupts 0-63 */
 #define OCTEON_IRQ_MSI_BIT0	152
-#define OCTEON_IRQ_MSI_LAST	(OCTEON_IRQ_MSI_BIT0 + 63)
+#define OCTEON_IRQ_MSI_LAST	(OCTEON_IRQ_MSI_BIT0 + 255)
 
 #define OCTEON_IRQ_LAST		(OCTEON_IRQ_MSI_LAST + 1)
 #else