unicore32: modify io_p2v and io_v2p macros, and adjust PKUNITY_mmio_B…

…ASEs

1. remove __REG macro
2. add (void __iomem *) to io_p2v macro
3. add (phys_addr_t) to io_v2p macro
4. add PKUNITY_AHB_BASE and PKUNITY_APB_BASE definitions
5. modify all PKUNITY_mmio_BASEs from physical addr to virtual addr
6. adjust prefix macro for all usage of PKUNITY_mmio_BASEs
  -- by advice with Arnd Bergmann

Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>

arch/unicore32/include/asm/io.h

@@ -18,7 +18,7 @@
 #include <asm/memory.h>
 #include <asm/system.h>
 
-#define PCI_IOBASE	io_p2v(PKUNITY_PCILIO_BASE)
+#define PCI_IOBASE	PKUNITY_PCILIO_BASE
 #include <asm-generic/io.h>
 
 /*

arch/unicore32/include/mach/PKUnity.h

@@ -22,83 +22,87 @@
  */
 #define PKUNITY_SDRAM_BASE		0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */
 #define PKUNITY_MMIO_BASE		0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */
-#define PKUNITY_PCI_BASE		0x80000000 /* 0x80000000 - 0xBFFFFFFF 1GB */
-#include "regs-pci.h"
-#define PKUNITY_BOOT_ROM2_BASE		0xF4000000 /* 0xF4000000 - 0xF7FFFFFF 64MB */
-#define PKUNITY_BOOT_SRAM2_BASE		0xF8000000 /* 0xF8000000 - 0xFBFFFFFF 64MB */
-#define PKUNITY_BOOT_FLASH_BASE		0xFC000000 /* 0xFC000000 - 0xFFFFFFFF 64MB */
 
 /*
  * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB)
+ *	0x0D000000 - 0x0DFFFFFF 16MB: for UVC
+ *	0x0E000000 - 0x0EFFFFFF 16MB: for UNIGFX
  */
-#define PKUNITY_UVC_MMAP_BASE		0x0D000000 /* 0x0D000000 - 0x0DFFFFFF 16MB */
+#define PKUNITY_UVC_MMAP_BASE		0x0D000000
 #define PKUNITY_UVC_MMAP_SIZE		0x01000000 /* 16MB */
-#define PKUNITY_UNIGFX_MMAP_BASE        0x0E000000 /* 0x0E000000 - 0x0EFFFFFF 16MB */
+#define PKUNITY_UNIGFX_MMAP_BASE        0x0E000000
 #define PKUNITY_UNIGFX_MMAP_SIZE        0x01000000 /* 16MB */
 
 /*
  * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB)
+ * 0x80000000 - 0x8000000B 12B    PCI Configuration regs
+ * 0x80010000 - 0x80010250 592B   PCI Bridge Base
+ * 0x80030000 - 0x8003FFFF 64KB   PCI Legacy IO
+ * 0x90000000 - 0x97FFFFFF 128MB  PCI AHB-PCI MEM-mapping
+ * 0x98000000 - 0x9FFFFFFF 128MB  PCI PCI-AHB MEM-mapping
  */
-/* PCI Configuration regs */
-#define PKUNITY_PCICFG_BASE             0x80000000 /* 0x80000000 - 0x8000000B 12B */
-/* PCI Bridge Base */
-#define PKUNITY_PCIBRI_BASE             0x80010000 /* 0x80010000 - 0x80010250 592B */
-/* PCI Legacy IO */
-#define PKUNITY_PCILIO_BASE             0x80030000 /* 0x80030000 - 0x8003FFFF 64KB */
-/* PCI AHB-PCI MEM-mapping */
-#define PKUNITY_PCIMEM_BASE             0x90000000 /* 0x90000000 - 0x97FFFFFF 128MB */
-/* PCI PCI-AHB MEM-mapping */
-#define PKUNITY_PCIAHB_BASE             0x98000000 /* 0x98000000 - 0x9FFFFFFF 128MB */
+#define PKUNITY_PCI_BASE		io_p2v(0x80000000) /* 0x80000000 - 0xBFFFFFFF 1GB */
+#include "regs-pci.h"
+
+#define PKUNITY_PCICFG_BASE		(PKUNITY_PCI_BASE + 0x0)
+#define PKUNITY_PCIBRI_BASE		(PKUNITY_PCI_BASE + 0x00010000)
+#define PKUNITY_PCILIO_BASE		(PKUNITY_PCI_BASE + 0x00030000)
+#define PKUNITY_PCIMEM_BASE		(PKUNITY_PCI_BASE + 0x10000000)
+#define PKUNITY_PCIAHB_BASE		(PKUNITY_PCI_BASE + 0x18000000)
 
 /*
  * PKUNITY System Bus Addresses (AHB): 0xC0000000 - 0xEDFFFFFF (640MB)
  */
+#define PKUNITY_AHB_BASE		io_p2v(0xC0000000)
+
 /* AHB-0 is DDR2 SDRAM */
 /* AHB-1 is PCI Space */
-#define PKUNITY_ARBITER_BASE		0xC0000000 /* AHB-2 */
-#define PKUNITY_DDR2CTRL_BASE		0xC0100000 /* AHB-3 */
-#define PKUNITY_DMAC_BASE		0xC0200000 /* AHB-4 */
+#define PKUNITY_ARBITER_BASE		(PKUNITY_AHB_BASE + 0x000000) /* AHB-2 */
+#define PKUNITY_DDR2CTRL_BASE		(PKUNITY_AHB_BASE + 0x100000) /* AHB-3 */
+#define PKUNITY_DMAC_BASE		(PKUNITY_AHB_BASE + 0x200000) /* AHB-4 */
 #include "regs-dmac.h"
-#define PKUNITY_UMAL_BASE		0xC0300000 /* AHB-5 */
+#define PKUNITY_UMAL_BASE		(PKUNITY_AHB_BASE + 0x300000) /* AHB-5 */
 #include "regs-umal.h"
-#define PKUNITY_USB_BASE		0xC0400000 /* AHB-6 */
-#define PKUNITY_SATA_BASE		0xC0500000 /* AHB-7 */
-#define PKUNITY_SMC_BASE		0xC0600000 /* AHB-8 */
+#define PKUNITY_USB_BASE		(PKUNITY_AHB_BASE + 0x400000) /* AHB-6 */
+#define PKUNITY_SATA_BASE		(PKUNITY_AHB_BASE + 0x500000) /* AHB-7 */
+#define PKUNITY_SMC_BASE		(PKUNITY_AHB_BASE + 0x600000) /* AHB-8 */
 /* AHB-9 is for APB bridge */
-#define PKUNITY_MME_BASE		0xC0700000 /* AHB-10 */
-#define PKUNITY_UNIGFX_BASE		0xC0800000 /* AHB-11 */
+#define PKUNITY_MME_BASE		(PKUNITY_AHB_BASE + 0x700000) /* AHB-10 */
+#define PKUNITY_UNIGFX_BASE		(PKUNITY_AHB_BASE + 0x800000) /* AHB-11 */
 #include "regs-unigfx.h"
-#define PKUNITY_NAND_BASE		0xC0900000 /* AHB-12 */
+#define PKUNITY_NAND_BASE		(PKUNITY_AHB_BASE + 0x900000) /* AHB-12 */
 #include "regs-nand.h"
-#define PKUNITY_H264D_BASE		0xC0A00000 /* AHB-13 */
-#define PKUNITY_H264E_BASE		0xC0B00000 /* AHB-14 */
+#define PKUNITY_H264D_BASE		(PKUNITY_AHB_BASE + 0xA00000) /* AHB-13 */
+#define PKUNITY_H264E_BASE		(PKUNITY_AHB_BASE + 0xB00000) /* AHB-14 */
 
 /*
  * PKUNITY Peripheral Bus Addresses (APB): 0xEE000000 - 0xEFFFFFFF (128MB)
  */
-#define PKUNITY_UART0_BASE		0xEE000000 /* APB-0 */
-#define PKUNITY_UART1_BASE		0xEE100000 /* APB-1 */
+#define PKUNITY_APB_BASE		io_p2v(0xEE000000)
+
+#define PKUNITY_UART0_BASE		(PKUNITY_APB_BASE + 0x000000) /* APB-0 */
+#define PKUNITY_UART1_BASE		(PKUNITY_APB_BASE + 0x100000) /* APB-1 */
 #include "regs-uart.h"
-#define PKUNITY_I2C_BASE		0xEE200000 /* APB-2 */
+#define PKUNITY_I2C_BASE		(PKUNITY_APB_BASE + 0x200000) /* APB-2 */
 #include "regs-i2c.h"
-#define PKUNITY_SPI_BASE		0xEE300000 /* APB-3 */
+#define PKUNITY_SPI_BASE		(PKUNITY_APB_BASE + 0x300000) /* APB-3 */
 #include "regs-spi.h"
-#define PKUNITY_AC97_BASE		0xEE400000 /* APB-4 */
+#define PKUNITY_AC97_BASE		(PKUNITY_APB_BASE + 0x400000) /* APB-4 */
 #include "regs-ac97.h"
-#define PKUNITY_GPIO_BASE		0xEE500000 /* APB-5 */
+#define PKUNITY_GPIO_BASE		(PKUNITY_APB_BASE + 0x500000) /* APB-5 */
 #include "regs-gpio.h"
-#define PKUNITY_INTC_BASE		0xEE600000 /* APB-6 */
+#define PKUNITY_INTC_BASE		(PKUNITY_APB_BASE + 0x600000) /* APB-6 */
 #include "regs-intc.h"
-#define PKUNITY_RTC_BASE		0xEE700000 /* APB-7 */
+#define PKUNITY_RTC_BASE		(PKUNITY_APB_BASE + 0x700000) /* APB-7 */
 #include "regs-rtc.h"
-#define PKUNITY_OST_BASE		0xEE800000 /* APB-8 */
+#define PKUNITY_OST_BASE		(PKUNITY_APB_BASE + 0x800000) /* APB-8 */
 #include "regs-ost.h"
-#define PKUNITY_RESETC_BASE		0xEE900000 /* APB-9 */
+#define PKUNITY_RESETC_BASE		(PKUNITY_APB_BASE + 0x900000) /* APB-9 */
 #include "regs-resetc.h"
-#define PKUNITY_PM_BASE			0xEEA00000 /* APB-10 */
+#define PKUNITY_PM_BASE			(PKUNITY_APB_BASE + 0xA00000) /* APB-10 */
 #include "regs-pm.h"
-#define PKUNITY_PS2_BASE		0xEEB00000 /* APB-11 */
+#define PKUNITY_PS2_BASE		(PKUNITY_APB_BASE + 0xB00000) /* APB-11 */
 #include "regs-ps2.h"
-#define PKUNITY_SDC_BASE		0xEEC00000 /* APB-12 */
+#define PKUNITY_SDC_BASE		(PKUNITY_APB_BASE + 0xC00000) /* APB-12 */
 #include "regs-sdc.h"
 

arch/unicore32/include/mach/hardware.h

@@ -17,17 +17,16 @@
 
 #include "PKUnity.h"
 
+#ifndef __ASSEMBLY__
+#define io_p2v(x)	(void __iomem *)((x) - PKUNITY_MMIO_BASE)
+#define io_v2p(x)	(phys_addr_t)((x) + PKUNITY_MMIO_BASE)
+#else
 #define io_p2v(x)	((x) - PKUNITY_MMIO_BASE)
 #define io_v2p(x)	((x) + PKUNITY_MMIO_BASE)
-
-#ifndef __ASSEMBLY__
-
-# define __REG(x)	(void __iomem *)io_p2v(x)
-
 #endif
 
 #define PCIBIOS_MIN_IO			0x4000 /* should lower than 64KB */
-#define PCIBIOS_MIN_MEM			PKUNITY_PCIMEM_BASE
+#define PCIBIOS_MIN_MEM			io_v2p(PKUNITY_PCIMEM_BASE)
 
 /*
  * We override the standard dma-mask routines for bouncing.

arch/unicore32/include/mach/memory.h

@@ -45,8 +45,8 @@ void puv3_pci_adjust_zones(unsigned long *size, unsigned long *holes);
 #define is_pcibus_device(dev)	(dev &&			\
 				(strncmp(dev->bus->name, "pci", 3) == 0))
 
-#define __virt_to_pcibus(x)     (__virt_to_phys(x) + PKUNITY_PCIAHB_BASE)
-#define __pcibus_to_virt(x)     __phys_to_virt((x) - PKUNITY_PCIAHB_BASE)
+#define __virt_to_pcibus(x)     (__virt_to_phys((x) + PKUNITY_PCIAHB_BASE))
+#define __pcibus_to_virt(x)     (__phys_to_virt(x) - PKUNITY_PCIAHB_BASE)
 
 /* kuser area */
 #define KUSER_VECPAGE_BASE	(KUSER_BASE + UL(0x3fff0000))

arch/unicore32/include/mach/regs-ac97.h

@@ -2,16 +2,16 @@
  * PKUnity AC97 Registers
  */
 
-#define PKUNITY_AC97_CONR		__REG(PKUNITY_AC97_BASE + 0x0000)
-#define PKUNITY_AC97_OCR		__REG(PKUNITY_AC97_BASE + 0x0004)
-#define PKUNITY_AC97_ICR		__REG(PKUNITY_AC97_BASE + 0x0008)
-#define PKUNITY_AC97_CRAC		__REG(PKUNITY_AC97_BASE + 0x000C)
-#define PKUNITY_AC97_INTR		__REG(PKUNITY_AC97_BASE + 0x0010)
-#define PKUNITY_AC97_INTRSTAT		__REG(PKUNITY_AC97_BASE + 0x0014)
-#define PKUNITY_AC97_INTRCLEAR		__REG(PKUNITY_AC97_BASE + 0x0018)
-#define PKUNITY_AC97_ENABLE		__REG(PKUNITY_AC97_BASE + 0x001C)
-#define PKUNITY_AC97_OUT_FIFO		__REG(PKUNITY_AC97_BASE + 0x0020)
-#define PKUNITY_AC97_IN_FIFO		__REG(PKUNITY_AC97_BASE + 0x0030)
+#define PKUNITY_AC97_CONR		(PKUNITY_AC97_BASE + 0x0000)
+#define PKUNITY_AC97_OCR		(PKUNITY_AC97_BASE + 0x0004)
+#define PKUNITY_AC97_ICR		(PKUNITY_AC97_BASE + 0x0008)
+#define PKUNITY_AC97_CRAC		(PKUNITY_AC97_BASE + 0x000C)
+#define PKUNITY_AC97_INTR		(PKUNITY_AC97_BASE + 0x0010)
+#define PKUNITY_AC97_INTRSTAT		(PKUNITY_AC97_BASE + 0x0014)
+#define PKUNITY_AC97_INTRCLEAR		(PKUNITY_AC97_BASE + 0x0018)
+#define PKUNITY_AC97_ENABLE		(PKUNITY_AC97_BASE + 0x001C)
+#define PKUNITY_AC97_OUT_FIFO		(PKUNITY_AC97_BASE + 0x0020)
+#define PKUNITY_AC97_IN_FIFO		(PKUNITY_AC97_BASE + 0x0030)
 
 #define AC97_CODEC_REG(v)               FIELD((v), 7, 16)
 #define AC97_CODEC_VAL(v)               FIELD((v), 16, 0)

arch/unicore32/include/mach/regs-dmac.h

@@ -5,27 +5,27 @@
 /*
  * Interrupt Status Reg DMAC_ISR.
  */
-#define DMAC_ISR		__REG(PKUNITY_DMAC_BASE + 0x0020)
+#define DMAC_ISR		(PKUNITY_DMAC_BASE + 0x0020)
 /*
  * Interrupt Transfer Complete Status Reg DMAC_ITCSR.
  */
-#define DMAC_ITCSR		__REG(PKUNITY_DMAC_BASE + 0x0050)
+#define DMAC_ITCSR		(PKUNITY_DMAC_BASE + 0x0050)
 /*
  * Interrupt Transfer Complete Clear Reg DMAC_ITCCR.
  */
-#define DMAC_ITCCR		__REG(PKUNITY_DMAC_BASE + 0x0060)
+#define DMAC_ITCCR		(PKUNITY_DMAC_BASE + 0x0060)
 /*
  * Interrupt Error Status Reg DMAC_IESR.
  */
-#define DMAC_IESR		__REG(PKUNITY_DMAC_BASE + 0x0080)
+#define DMAC_IESR		(PKUNITY_DMAC_BASE + 0x0080)
 /*
  * Interrupt Error Clear Reg DMAC_IECR.
  */
-#define DMAC_IECR		__REG(PKUNITY_DMAC_BASE + 0x0090)
+#define DMAC_IECR		(PKUNITY_DMAC_BASE + 0x0090)
 /*
  * Enable Channels Reg DMAC_ENCH.
  */
-#define DMAC_ENCH		__REG(PKUNITY_DMAC_BASE + 0x00B0)
+#define DMAC_ENCH		(PKUNITY_DMAC_BASE + 0x00B0)
 
 /*
  * DMA control reg. Space [byte]
@@ -35,19 +35,19 @@
 /*
  * Source Addr DMAC_SRCADDR(ch).
  */
-#define DMAC_SRCADDR(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
+#define DMAC_SRCADDR(ch)	(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
 /*
  * Destination Addr DMAC_DESTADDR(ch).
  */
-#define DMAC_DESTADDR(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
+#define DMAC_DESTADDR(ch)	(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
 /*
  * Control Reg DMAC_CONTROL(ch).
  */
-#define DMAC_CONTROL(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
+#define DMAC_CONTROL(ch)	(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
 /*
  * Configuration Reg DMAC_CONFIG(ch).
  */
-#define DMAC_CONFIG(ch)		__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
+#define DMAC_CONFIG(ch)		(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
 
 #define DMAC_IR_MASK            FMASK(6, 0)
 /*

arch/unicore32/include/mach/regs-gpio.h

@@ -5,35 +5,35 @@
 /*
  * Voltage Status Reg GPIO_GPLR.
  */
-#define GPIO_GPLR	__REG(PKUNITY_GPIO_BASE + 0x0000)
+#define GPIO_GPLR	(PKUNITY_GPIO_BASE + 0x0000)
 /*
  * Pin Direction Reg GPIO_GPDR.
  */
-#define GPIO_GPDR	__REG(PKUNITY_GPIO_BASE + 0x0004)
+#define GPIO_GPDR	(PKUNITY_GPIO_BASE + 0x0004)
 /*
  * Output Pin Set Reg GPIO_GPSR.
  */
-#define GPIO_GPSR	__REG(PKUNITY_GPIO_BASE + 0x0008)
+#define GPIO_GPSR	(PKUNITY_GPIO_BASE + 0x0008)
 /*
  * Output Pin Clear Reg GPIO_GPCR.
  */
-#define GPIO_GPCR	__REG(PKUNITY_GPIO_BASE + 0x000C)
+#define GPIO_GPCR	(PKUNITY_GPIO_BASE + 0x000C)
 /*
  * Raise Edge Detect Reg GPIO_GRER.
  */
-#define GPIO_GRER	__REG(PKUNITY_GPIO_BASE + 0x0010)
+#define GPIO_GRER	(PKUNITY_GPIO_BASE + 0x0010)
 /*
  * Fall Edge Detect Reg GPIO_GFER.
  */
-#define GPIO_GFER	__REG(PKUNITY_GPIO_BASE + 0x0014)
+#define GPIO_GFER	(PKUNITY_GPIO_BASE + 0x0014)
 /*
  * Edge Status Reg GPIO_GEDR.
  */
-#define GPIO_GEDR	__REG(PKUNITY_GPIO_BASE + 0x0018)
+#define GPIO_GEDR	(PKUNITY_GPIO_BASE + 0x0018)
 /*
  * Sepcial Voltage Detect Reg GPIO_GPIR.
  */
-#define GPIO_GPIR	__REG(PKUNITY_GPIO_BASE + 0x0020)
+#define GPIO_GPIR	(PKUNITY_GPIO_BASE + 0x0020)
 
 #define GPIO_MIN	(0)
 #define GPIO_MAX	(27)

arch/unicore32/include/mach/regs-i2c.h

@@ -5,35 +5,35 @@
 /*
  * Control Reg I2C_CON.
  */
-#define I2C_CON		__REG(PKUNITY_I2C_BASE + 0x0000)
+#define I2C_CON		(PKUNITY_I2C_BASE + 0x0000)
 /*
  * Target Address Reg I2C_TAR.
  */
-#define I2C_TAR		__REG(PKUNITY_I2C_BASE + 0x0004)
+#define I2C_TAR		(PKUNITY_I2C_BASE + 0x0004)
 /*
  * Data buffer and command Reg I2C_DATACMD.
  */
-#define I2C_DATACMD	__REG(PKUNITY_I2C_BASE + 0x0010)
+#define I2C_DATACMD	(PKUNITY_I2C_BASE + 0x0010)
 /*
  * Enable Reg I2C_ENABLE.
  */
-#define I2C_ENABLE	__REG(PKUNITY_I2C_BASE + 0x006C)
+#define I2C_ENABLE	(PKUNITY_I2C_BASE + 0x006C)
 /*
  * Status Reg I2C_STATUS.
  */
-#define I2C_STATUS	__REG(PKUNITY_I2C_BASE + 0x0070)
+#define I2C_STATUS	(PKUNITY_I2C_BASE + 0x0070)
 /*
  * Tx FIFO Length Reg I2C_TXFLR.
  */
-#define I2C_TXFLR	__REG(PKUNITY_I2C_BASE + 0x0074)
+#define I2C_TXFLR	(PKUNITY_I2C_BASE + 0x0074)
 /*
  * Rx FIFO Length Reg I2C_RXFLR.
  */
-#define I2C_RXFLR	__REG(PKUNITY_I2C_BASE + 0x0078)
+#define I2C_RXFLR	(PKUNITY_I2C_BASE + 0x0078)
 /*
  * Enable Status Reg I2C_ENSTATUS.
  */
-#define I2C_ENSTATUS	__REG(PKUNITY_I2C_BASE + 0x009C)
+#define I2C_ENSTATUS	(PKUNITY_I2C_BASE + 0x009C)
 
 #define I2C_CON_MASTER          FIELD(1, 1, 0)
 #define I2C_CON_SPEED_STD       FIELD(1, 2, 1)

arch/unicore32/include/mach/regs-intc.h

@@ -4,25 +4,25 @@
 /*
  * INTC Level Reg INTC_ICLR.
  */
-#define INTC_ICLR	__REG(PKUNITY_INTC_BASE + 0x0000)
+#define INTC_ICLR	(PKUNITY_INTC_BASE + 0x0000)
 /*
  * INTC Mask Reg INTC_ICMR.
  */
-#define INTC_ICMR	__REG(PKUNITY_INTC_BASE + 0x0004)
+#define INTC_ICMR	(PKUNITY_INTC_BASE + 0x0004)
 /*
  * INTC Pending Reg INTC_ICPR.
  */
-#define INTC_ICPR	__REG(PKUNITY_INTC_BASE + 0x0008)
+#define INTC_ICPR	(PKUNITY_INTC_BASE + 0x0008)
 /*
  * INTC IRQ Pending Reg INTC_ICIP.
  */
-#define INTC_ICIP	__REG(PKUNITY_INTC_BASE + 0x000C)
+#define INTC_ICIP	(PKUNITY_INTC_BASE + 0x000C)
 /*
  * INTC REAL Pending Reg INTC_ICFP.
  */
-#define INTC_ICFP	__REG(PKUNITY_INTC_BASE + 0x0010)
+#define INTC_ICFP	(PKUNITY_INTC_BASE + 0x0010)
 /*
  * INTC Control Reg INTC_ICCR.
  */
-#define INTC_ICCR	__REG(PKUNITY_INTC_BASE + 0x0014)
+#define INTC_ICCR	(PKUNITY_INTC_BASE + 0x0014)