Skip to content

Commit

Permalink
ARM: 6418/1: ux500: rename DB8500 DMA event line macros
Browse files Browse the repository at this point in the history 
Change the DMA event line macros to have the name of the SoC.  Also,
have the event line number encoded in the macro since on DB5500 several
event lines are present at multiple alternate numbers.

Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
  • Loading branch information
Rabin Vincent authored and Russell King committed Oct 4, 2010
1 parent e81fcc9 commit 1d7e356
Show file tree
Hide file tree
Showing 2 changed files with 133 additions and 143 deletions.
18 changes: 9 additions & 9 deletions arch/arm/mach-ux500/devices-db8500.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -246,23 +246,23 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
* Mapping between destination event lines and physical device address.
* The event line is tied to a device and therefor the address is constant.
*/
static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV];
static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV];

/* Mapping between source event lines and physical device address */
static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV];
static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV];

/* Reserved event lines for memcpy only */
static int dma40_memcpy_event[] = {
STEDMA40_MEMCPY_TX_0,
STEDMA40_MEMCPY_TX_1,
STEDMA40_MEMCPY_TX_2,
STEDMA40_MEMCPY_TX_3,
STEDMA40_MEMCPY_TX_4,
STEDMA40_MEMCPY_TX_5,
DB8500_DMA_MEMCPY_TX_0,
DB8500_DMA_MEMCPY_TX_1,
DB8500_DMA_MEMCPY_TX_2,
DB8500_DMA_MEMCPY_TX_3,
DB8500_DMA_MEMCPY_TX_4,
DB8500_DMA_MEMCPY_TX_5,
};

static struct stedma40_platform_data dma40_plat_data = {
.dev_len = STEDMA40_NR_DEV,
.dev_len = DB8500_DMA_NR_DEV,
.dev_rx = dma40_rx_map,
.dev_tx = dma40_tx_map,
.memcpy = dma40_memcpy_event,
Expand Down
258 changes: 124 additions & 134 deletions arch/arm/mach-ux500/ste-dma40-db8500.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,145 +10,135 @@
#ifndef STE_DMA40_DB8500_H
#define STE_DMA40_DB8500_H

#define STEDMA40_NR_DEV 64
#define DB8500_DMA_NR_DEV 64

enum dma_src_dev_type {
STEDMA40_DEV_SPI0_RX = 0,
STEDMA40_DEV_SD_MMC0_RX = 1,
STEDMA40_DEV_SD_MMC1_RX = 2,
STEDMA40_DEV_SD_MMC2_RX = 3,
STEDMA40_DEV_I2C1_RX = 4,
STEDMA40_DEV_I2C3_RX = 5,
STEDMA40_DEV_I2C2_RX = 6,
STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */
STEDMA40_DEV_SSP0_RX = 8,
STEDMA40_DEV_SSP1_RX = 9,
STEDMA40_DEV_MCDE_RX = 10,
STEDMA40_DEV_UART2_RX = 11,
STEDMA40_DEV_UART1_RX = 12,
STEDMA40_DEV_UART0_RX = 13,
STEDMA40_DEV_MSP2_RX = 14,
STEDMA40_DEV_I2C0_RX = 15,
STEDMA40_DEV_USB_OTG_IEP_8 = 16,
STEDMA40_DEV_USB_OTG_IEP_1_9 = 17,
STEDMA40_DEV_USB_OTG_IEP_2_10 = 18,
STEDMA40_DEV_USB_OTG_IEP_3_11 = 19,
STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
STEDMA40_DEV_SRC_SXA0_RX_TX = 24,
STEDMA40_DEV_SRC_SXA1_RX_TX = 25,
STEDMA40_DEV_SRC_SXA2_RX_TX = 26,
STEDMA40_DEV_SRC_SXA3_RX_TX = 27,
STEDMA40_DEV_SD_MM2_RX = 28,
STEDMA40_DEV_SD_MM0_RX = 29,
STEDMA40_DEV_MSP1_RX = 30,
/*
* This channel is either SlimBus or MSP,
* never both at the same time.
*/
STEDMA40_SLIM0_CH0_RX = 31,
STEDMA40_DEV_MSP0_RX = 31,
STEDMA40_DEV_SD_MM1_RX = 32,
STEDMA40_DEV_SPI2_RX = 33,
STEDMA40_DEV_I2C3_RX2 = 34,
STEDMA40_DEV_SPI1_RX = 35,
STEDMA40_DEV_USB_OTG_IEP_4_12 = 36,
STEDMA40_DEV_USB_OTG_IEP_5_13 = 37,
STEDMA40_DEV_USB_OTG_IEP_6_14 = 38,
STEDMA40_DEV_USB_OTG_IEP_7_15 = 39,
STEDMA40_DEV_SPI3_RX = 40,
STEDMA40_DEV_SD_MM3_RX = 41,
STEDMA40_DEV_SD_MM4_RX = 42,
STEDMA40_DEV_SD_MM5_RX = 43,
STEDMA40_DEV_SRC_SXA4_RX_TX = 44,
STEDMA40_DEV_SRC_SXA5_RX_TX = 45,
STEDMA40_DEV_SRC_SXA6_RX_TX = 46,
STEDMA40_DEV_SRC_SXA7_RX_TX = 47,
STEDMA40_DEV_CAC1_RX = 48,
/* RX channels 49 and 50 are unused */
STEDMA40_DEV_MSHC_RX = 51,
STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52,
STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53,
STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54,
STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55,
/* RX channels 56 thru 60 are unused */
STEDMA40_DEV_CAC0_RX = 61,
/* RX channels 62 and 63 are unused */
DB8500_DMA_DEV0_SPI0_RX = 0,
DB8500_DMA_DEV1_SD_MMC0_RX = 1,
DB8500_DMA_DEV2_SD_MMC1_RX = 2,
DB8500_DMA_DEV3_SD_MMC2_RX = 3,
DB8500_DMA_DEV4_I2C1_RX = 4,
DB8500_DMA_DEV5_I2C3_RX = 5,
DB8500_DMA_DEV6_I2C2_RX = 6,
DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
DB8500_DMA_DEV8_SSP0_RX = 8,
DB8500_DMA_DEV9_SSP1_RX = 9,
DB8500_DMA_DEV10_MCDE_RX = 10,
DB8500_DMA_DEV11_UART2_RX = 11,
DB8500_DMA_DEV12_UART1_RX = 12,
DB8500_DMA_DEV13_UART0_RX = 13,
DB8500_DMA_DEV14_MSP2_RX = 14,
DB8500_DMA_DEV15_I2C0_RX = 15,
DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
DB8500_DMA_DEV28_SD_MM2_RX = 28,
DB8500_DMA_DEV29_SD_MM0_RX = 29,
DB8500_DMA_DEV30_MSP1_RX = 30,
/* On DB8500v2, MSP3 RX replaces MSP1 RX */
DB8500_DMA_DEV30_MSP3_RX = 30,
DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
DB8500_DMA_DEV32_SD_MM1_RX = 32,
DB8500_DMA_DEV33_SPI2_RX = 33,
DB8500_DMA_DEV34_I2C3_RX2 = 34,
DB8500_DMA_DEV35_SPI1_RX = 35,
DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
DB8500_DMA_DEV40_SPI3_RX = 40,
DB8500_DMA_DEV41_SD_MM3_RX = 41,
DB8500_DMA_DEV42_SD_MM4_RX = 42,
DB8500_DMA_DEV43_SD_MM5_RX = 43,
DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
DB8500_DMA_DEV48_CAC1_RX = 48,
/* 49, 50 and 51 are not used */
DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
/* 56, 57, 58, 59 and 60 are not used */
DB8500_DMA_DEV61_CAC0_RX = 61,
/* 62 and 63 are not used */
};

enum dma_dest_dev_type {
STEDMA40_DEV_SPI0_TX = 0,
STEDMA40_DEV_SD_MMC0_TX = 1,
STEDMA40_DEV_SD_MMC1_TX = 2,
STEDMA40_DEV_SD_MMC2_TX = 3,
STEDMA40_DEV_I2C1_TX = 4,
STEDMA40_DEV_I2C3_TX = 5,
STEDMA40_DEV_I2C2_TX = 6,
STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */
STEDMA40_DEV_SSP0_TX = 8,
STEDMA40_DEV_SSP1_TX = 9,
/* TX channel 10 is unused */
STEDMA40_DEV_UART2_TX = 11,
STEDMA40_DEV_UART1_TX = 12,
STEDMA40_DEV_UART0_TX= 13,
STEDMA40_DEV_MSP2_TX = 14,
STEDMA40_DEV_I2C0_TX = 15,
STEDMA40_DEV_USB_OTG_OEP_8 = 16,
STEDMA40_DEV_USB_OTG_OEP_1_9 = 17,
STEDMA40_DEV_USB_OTG_OEP_2_10= 18,
STEDMA40_DEV_USB_OTG_OEP_3_11 = 19,
STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
STEDMA40_DEV_DST_SXA0_RX_TX = 24,
STEDMA40_DEV_DST_SXA1_RX_TX = 25,
STEDMA40_DEV_DST_SXA2_RX_TX = 26,
STEDMA40_DEV_DST_SXA3_RX_TX = 27,
STEDMA40_DEV_SD_MM2_TX = 28,
STEDMA40_DEV_SD_MM0_TX = 29,
STEDMA40_DEV_MSP1_TX = 30,
/*
* This channel is either SlimBus or MSP,
* never both at the same time.
*/
STEDMA40_SLIM0_CH0_TX = 31,
STEDMA40_DEV_MSP0_TX = 31,
STEDMA40_DEV_SD_MM1_TX = 32,
STEDMA40_DEV_SPI2_TX = 33,
/* Secondary I2C3 channel */
STEDMA40_DEV_I2C3_TX2 = 34,
STEDMA40_DEV_SPI1_TX = 35,
STEDMA40_DEV_USB_OTG_OEP_4_12 = 36,
STEDMA40_DEV_USB_OTG_OEP_5_13 = 37,
STEDMA40_DEV_USB_OTG_OEP_6_14 = 38,
STEDMA40_DEV_USB_OTG_OEP_7_15 = 39,
STEDMA40_DEV_SPI3_TX = 40,
STEDMA40_DEV_SD_MM3_TX = 41,
STEDMA40_DEV_SD_MM4_TX = 42,
STEDMA40_DEV_SD_MM5_TX = 43,
STEDMA40_DEV_DST_SXA4_RX_TX = 44,
STEDMA40_DEV_DST_SXA5_RX_TX = 45,
STEDMA40_DEV_DST_SXA6_RX_TX = 46,
STEDMA40_DEV_DST_SXA7_RX_TX = 47,
STEDMA40_DEV_CAC1_TX = 48,
STEDMA40_DEV_CAC1_TX_HAC1_TX = 49,
STEDMA40_DEV_HAC1_TX = 50,
STEDMA40_MEMCPY_TX_0 = 51,
STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52,
STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53,
STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54,
STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55,
STEDMA40_MEMCPY_TX_1 = 56,
STEDMA40_MEMCPY_TX_2 = 57,
STEDMA40_MEMCPY_TX_3 = 58,
STEDMA40_MEMCPY_TX_4 = 59,
STEDMA40_MEMCPY_TX_5 = 60,
STEDMA40_DEV_CAC0_TX = 61,
STEDMA40_DEV_CAC0_TX_HAC0_TX = 62,
STEDMA40_DEV_HAC0_TX = 63,
DB8500_DMA_DEV0_SPI0_TX = 0,
DB8500_DMA_DEV1_SD_MMC0_TX = 1,
DB8500_DMA_DEV2_SD_MMC1_TX = 2,
DB8500_DMA_DEV3_SD_MMC2_TX = 3,
DB8500_DMA_DEV4_I2C1_TX = 4,
DB8500_DMA_DEV5_I2C3_TX = 5,
DB8500_DMA_DEV6_I2C2_TX = 6,
DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
DB8500_DMA_DEV8_SSP0_TX = 8,
DB8500_DMA_DEV9_SSP1_TX = 9,
/* 10 is not used*/
DB8500_DMA_DEV11_UART2_TX = 11,
DB8500_DMA_DEV12_UART1_TX = 12,
DB8500_DMA_DEV13_UART0_TX = 13,
DB8500_DMA_DEV14_MSP2_TX = 14,
DB8500_DMA_DEV15_I2C0_TX = 15,
DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
DB8500_DMA_DEV28_SD_MM2_TX = 28,
DB8500_DMA_DEV29_SD_MM0_TX = 29,
DB8500_DMA_DEV30_MSP1_TX = 30,
DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
DB8500_DMA_DEV32_SD_MM1_TX = 32,
DB8500_DMA_DEV33_SPI2_TX = 33,
DB8500_DMA_DEV34_I2C3_TX2 = 34,
DB8500_DMA_DEV35_SPI1_TX = 35,
DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
DB8500_DMA_DEV40_SPI3_TX = 40,
DB8500_DMA_DEV41_SD_MM3_TX = 41,
DB8500_DMA_DEV42_SD_MM4_TX = 42,
DB8500_DMA_DEV43_SD_MM5_TX = 43,
DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
DB8500_DMA_DEV48_CAC1_TX = 48,
DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
DB8500_DMA_DEV50_HAC1_TX = 50,
DB8500_DMA_MEMCPY_TX_0 = 51,
DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
DB8500_DMA_MEMCPY_TX_1 = 56,
DB8500_DMA_MEMCPY_TX_2 = 57,
DB8500_DMA_MEMCPY_TX_3 = 58,
DB8500_DMA_MEMCPY_TX_4 = 59,
DB8500_DMA_MEMCPY_TX_5 = 60,
DB8500_DMA_DEV61_CAC0_TX = 61,
DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
DB8500_DMA_DEV63_HAC0_TX = 63,
};

#endif

0 comments on commit 1d7e356

Please sign in to comment.