drm/amd/display: simplify link_encoder

- remove unnecessary feature flags
- remove wireless and VGA validation

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link.c

@@ -317,7 +317,6 @@ static bool is_dp_sink_present(struct core_link *link)
 {
 	enum gpio_result gpio_result;
 	uint32_t clock_pin = 0;
-	uint32_t data_pin = 0;
 
 	struct ddc *ddc;
 
@@ -353,12 +352,7 @@ static bool is_dp_sink_present(struct core_link *link)
 	gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 	ASSERT(gpio_result == GPIO_RESULT_OK);
 
-	if (gpio_result == GPIO_RESULT_OK)
-		if (link->link_enc->features.flags.bits.
-						DP_SINK_DETECT_POLL_DATA_PIN)
-			gpio_result = dal_gpio_get_value(ddc->pin_data, &data_pin);
-
-	present = (gpio_result == GPIO_RESULT_OK) && !(clock_pin || data_pin);
+	present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 
 	dal_ddc_close(ddc);
 

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

@@ -67,11 +67,6 @@
 #define HPD_REG(reg)\
 	(enc110->hpd_regs->reg)
 
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLK 600000
-
-#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 594000
-
 #define DEFAULT_AUX_MAX_DATA_SIZE 16
 #define AUX_MAX_DEFER_WRITE_RETRY 20
 /*
@@ -845,18 +840,15 @@ bool dce110_link_encoder_validate_dvi_output(
 {
 	uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
 
-	if (enc110->base.features.max_pixel_clock < TMDS_MAX_PIXEL_CLOCK)
-		max_pixel_clock = enc110->base.features.max_pixel_clock;
-
 	if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-		max_pixel_clock <<= 1;
+		max_pixel_clock *= 2;
 
 	/* This handles the case of HDMI downgrade to DVI we don't want to
 	 * we don't want to cap the pixel clock if the DDI is not DVI.
 	 */
 	if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
 			connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
-		max_pixel_clock = enc110->base.features.max_pixel_clock;
+		max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
 
 	/* DVI only support RGB pixel encoding */
 	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
@@ -893,18 +885,14 @@ static bool dce110_link_encoder_validate_hdmi_output(
 	enum dc_color_depth max_deep_color =
 			enc110->base.features.max_hdmi_deep_color;
 
-	if (max_deep_color > enc110->base.features.max_deep_color)
-		max_deep_color = enc110->base.features.max_deep_color;
-
 	if (max_deep_color < crtc_timing->display_color_depth)
 		return false;
 
 	if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
 		return false;
 
 	if ((adjusted_pix_clk_khz == 0) ||
-		(adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock) ||
-		(adjusted_pix_clk_khz > enc110->base.features.max_pixel_clock))
+		(adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
 		return false;
 
 	/* DCE11 HW does not support 420 */
@@ -915,19 +903,6 @@ static bool dce110_link_encoder_validate_hdmi_output(
 	return true;
 }
 
-bool dce110_link_encoder_validate_rgb_output(
-	const struct dce110_link_encoder *enc110,
-	const struct dc_crtc_timing *crtc_timing)
-{
-	if (crtc_timing->pix_clk_khz > enc110->base.features.max_pixel_clock)
-		return false;
-
-	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
-		return false;
-
-	return true;
-}
-
 bool dce110_link_encoder_validate_dp_output(
 	const struct dce110_link_encoder *enc110,
 	const struct dc_crtc_timing *crtc_timing)
@@ -949,21 +924,6 @@ bool dce110_link_encoder_validate_dp_output(
 	return false;
 }
 
-bool dce110_link_encoder_validate_wireless_output(
-	const struct dce110_link_encoder *enc110,
-	const struct dc_crtc_timing *crtc_timing)
-{
-	if (crtc_timing->pix_clk_khz > enc110->base.features.max_pixel_clock)
-		return false;
-
-	/* Wireless only supports YCbCr444 */
-	if (crtc_timing->pixel_encoding ==
-			PIXEL_ENCODING_YCBCR444)
-		return true;
-
-	return false;
-}
-
 bool dce110_link_encoder_construct(
 	struct dce110_link_encoder *enc110,
 	const struct encoder_init_data *init_data,
@@ -985,12 +945,6 @@ bool dce110_link_encoder_construct(
 
 	enc110->base.transmitter = init_data->transmitter;
 
-	enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
-
-	enc110->base.features.max_pixel_clock =
-			MAX_ENCODER_CLK;
-
-	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
 	enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
 
 	if (enc110->base.ctx->dc->debug.disable_hdmi_deep_color)
@@ -1070,7 +1024,6 @@ bool dce110_link_encoder_construct(
 				bp_cap_info.DP_HBR2_CAP;
 		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 				bp_cap_info.DP_HBR3_EN;
-
 	}
 
 	/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
@@ -1082,7 +1035,6 @@ bool dce110_link_encoder_construct(
 	/* test pattern 4 support */
 	enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
 
-	enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
 	/*
 		dal_adapter_service_is_feature_supported(as,
 			FEATURE_SUPPORT_DP_Y_ONLY);
@@ -1118,22 +1070,14 @@ bool dce110_link_encoder_validate_output_with_stream(
 				&stream->public.timing,
 				stream->phy_pix_clk);
 	break;
-	case SIGNAL_TYPE_RGB:
-		is_valid = dce110_link_encoder_validate_rgb_output(
-			enc110, &stream->public.timing);
-	break;
 	case SIGNAL_TYPE_DISPLAY_PORT:
 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 	case SIGNAL_TYPE_EDP:
 		is_valid = dce110_link_encoder_validate_dp_output(
 			enc110, &stream->public.timing);
 	break;
-	case SIGNAL_TYPE_WIRELESS:
-		is_valid = dce110_link_encoder_validate_wireless_output(
-			enc110, &stream->public.timing);
-	break;
 	default:
-		is_valid = true;
+		is_valid = false;
 	break;
 	}
 

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

@@ -33,34 +33,16 @@ struct encoder_init_data {
 struct encoder_feature_support {
 	union {
 		struct {
-			/* 1 - external encoder; 0 - internal encoder */
-			uint32_t EXTERNAL_ENCODER:1;
-			uint32_t ANALOG_ENCODER:1;
-			uint32_t STEREO_SYNC:1;
-			/* check the DDC data pin
-			 * when performing DP Sink detection */
-			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
-			/* CPLIB authentication
-			 * for external DP chip supported */
-			uint32_t CPLIB_DP_AUTHENTICATION:1;
 			uint32_t IS_HBR2_CAPABLE:1;
 			uint32_t IS_HBR3_CAPABLE:1;
-			uint32_t IS_HBR2_VALIDATED:1;
 			uint32_t IS_TPS3_CAPABLE:1;
 			uint32_t IS_TPS4_CAPABLE:1;
-			uint32_t IS_AUDIO_CAPABLE:1;
-			uint32_t IS_VCE_SUPPORTED:1;
-			uint32_t IS_CONVERTER:1;
-			uint32_t IS_Y_ONLY_CAPABLE:1;
 			uint32_t IS_YCBCR_CAPABLE:1;
 		} bits;
 		uint32_t raw;
 	} flags;
-	/* maximum supported deep color depth */
-	enum dc_color_depth max_deep_color;
+
 	enum dc_color_depth max_hdmi_deep_color;
-	/* maximum supported clock */
-	unsigned int max_pixel_clock;
 	unsigned int max_hdmi_pixel_clock;
 	bool ycbcr420_supported;
 };

drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c

@@ -28,8 +28,6 @@
 
 #include "virtual_link_encoder.h"
 
-#define VIRTUAL_MAX_PIXEL_CLK_IN_KHZ 600000
-
 static bool virtual_link_encoder_validate_output_with_stream(
 	struct link_encoder *enc,
 	struct pipe_ctx *pipe_ctx) { return true; }
@@ -138,8 +136,6 @@ bool virtual_link_encoder_construct(
 
 	enc->transmitter = init_data->transmitter;
 
-	enc->features.max_pixel_clock = VIRTUAL_MAX_PIXEL_CLK_IN_KHZ;
-
 	enc->output_signals = SIGNAL_TYPE_VIRTUAL;
 
 	enc->preferred_engine = ENGINE_ID_VIRTUAL;