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misc: xilinx_sdfec: Add ability to configure LDPC
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Add the capability to configure LDPC mode via the ioctl
XSDFEC_ADD_LDPC_CODE_PARAMS.

Tested-by: Dragan Cvetic <dragan.cvetic@xilinx.com>
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com>
Signed-off-by: Dragan Cvetic <dragan.cvetic@xilinx.com>
Link: https://lore.kernel.org/r/1564216438-322406-4-git-send-email-dragan.cvetic@xilinx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Dragan Cvetic authored and Greg Kroah-Hartman committed Aug 15, 2019
1 parent 6f86ed8 commit 20ec628
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324 changes: 324 additions & 0 deletions drivers/misc/xilinx_sdfec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/compat.h>
#include <linux/highmem.h>

#include <uapi/misc/xilinx_sdfec.h>

Expand Down Expand Up @@ -113,6 +114,57 @@ static struct mutex dev_idr_lock;
#define XSDFEC_TURBO_SCALE_BIT_POS (8)
#define XSDFEC_TURBO_SCALE_MAX (15)

/* REG0 Register */
#define XSDFEC_LDPC_CODE_REG0_ADDR_BASE (0x2000)
#define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH (0x27F0)
#define XSDFEC_REG0_N_MIN (4)
#define XSDFEC_REG0_N_MAX (32768)
#define XSDFEC_REG0_N_MUL_P (256)
#define XSDFEC_REG0_N_LSB (0)
#define XSDFEC_REG0_K_MIN (2)
#define XSDFEC_REG0_K_MAX (32766)
#define XSDFEC_REG0_K_MUL_P (256)
#define XSDFEC_REG0_K_LSB (16)

/* REG1 Register */
#define XSDFEC_LDPC_CODE_REG1_ADDR_BASE (0x2004)
#define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH (0x27f4)
#define XSDFEC_REG1_PSIZE_MIN (2)
#define XSDFEC_REG1_PSIZE_MAX (512)
#define XSDFEC_REG1_NO_PACKING_MASK (0x400)
#define XSDFEC_REG1_NO_PACKING_LSB (10)
#define XSDFEC_REG1_NM_MASK (0xFF800)
#define XSDFEC_REG1_NM_LSB (11)
#define XSDFEC_REG1_BYPASS_MASK (0x100000)

/* REG2 Register */
#define XSDFEC_LDPC_CODE_REG2_ADDR_BASE (0x2008)
#define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH (0x27f8)
#define XSDFEC_REG2_NLAYERS_MIN (1)
#define XSDFEC_REG2_NLAYERS_MAX (256)
#define XSDFEC_REG2_NNMQC_MASK (0xFFE00)
#define XSDFEC_REG2_NMQC_LSB (9)
#define XSDFEC_REG2_NORM_TYPE_MASK (0x100000)
#define XSDFEC_REG2_NORM_TYPE_LSB (20)
#define XSDFEC_REG2_SPECIAL_QC_MASK (0x200000)
#define XSDFEC_REG2_SPEICAL_QC_LSB (21)
#define XSDFEC_REG2_NO_FINAL_PARITY_MASK (0x400000)
#define XSDFEC_REG2_NO_FINAL_PARITY_LSB (22)
#define XSDFEC_REG2_MAX_SCHEDULE_MASK (0x1800000)
#define XSDFEC_REG2_MAX_SCHEDULE_LSB (23)

/* REG3 Register */
#define XSDFEC_LDPC_CODE_REG3_ADDR_BASE (0x200C)
#define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH (0x27FC)
#define XSDFEC_REG3_LA_OFF_LSB (8)
#define XSDFEC_REG3_QC_OFF_LSB (16)

#define XSDFEC_LDPC_REG_JUMP (0x10)
#define XSDFEC_REG_WIDTH_JUMP (4)

/* The maximum number of pinned pages */
#define MAX_NUM_PAGES ((XSDFEC_QC_TABLE_DEPTH / PAGE_SIZE) + 1)

/**
* struct xsdfec_clks - For managing SD-FEC clocks
* @core_clk: Main processing clock for core
Expand Down Expand Up @@ -270,6 +322,275 @@ static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg)
return err;
}

static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize,
u32 offset)
{
u32 wdata;

if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX ||
(n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) {
dev_dbg(xsdfec->dev, "N value is not in range");
return -EINVAL;
}
n <<= XSDFEC_REG0_N_LSB;

if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX ||
(k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) {
dev_dbg(xsdfec->dev, "K value is not in range");
return -EINVAL;
}
k = k << XSDFEC_REG0_K_LSB;
wdata = k | n;

if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) {
dev_dbg(xsdfec->dev, "Writing outside of LDPC reg0 space 0x%x",
XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP));
return -EINVAL;
}
xsdfec_regwrite(xsdfec,
XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP),
wdata);
return 0;
}

static int xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize,
u32 no_packing, u32 nm, u32 offset)
{
u32 wdata;

if (psize < XSDFEC_REG1_PSIZE_MIN || psize > XSDFEC_REG1_PSIZE_MAX) {
dev_dbg(xsdfec->dev, "Psize is not in range");
return -EINVAL;
}

if (no_packing != 0 && no_packing != 1)
dev_dbg(xsdfec->dev, "No-packing bit register invalid");
no_packing = ((no_packing << XSDFEC_REG1_NO_PACKING_LSB) &
XSDFEC_REG1_NO_PACKING_MASK);

if (nm & ~(XSDFEC_REG1_NM_MASK >> XSDFEC_REG1_NM_LSB))
dev_dbg(xsdfec->dev, "NM is beyond 10 bits");
nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK;

wdata = nm | no_packing | psize;
if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) {
dev_dbg(xsdfec->dev, "Writing outside of LDPC reg1 space 0x%x",
XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP));
return -EINVAL;
}
xsdfec_regwrite(xsdfec,
XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP),
wdata);
return 0;
}

static int xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc,
u32 norm_type, u32 special_qc, u32 no_final_parity,
u32 max_schedule, u32 offset)
{
u32 wdata;

if (nlayers < XSDFEC_REG2_NLAYERS_MIN ||
nlayers > XSDFEC_REG2_NLAYERS_MAX) {
dev_dbg(xsdfec->dev, "Nlayers is not in range");
return -EINVAL;
}

if (nmqc & ~(XSDFEC_REG2_NNMQC_MASK >> XSDFEC_REG2_NMQC_LSB))
dev_dbg(xsdfec->dev, "NMQC exceeds 11 bits");
nmqc = (nmqc << XSDFEC_REG2_NMQC_LSB) & XSDFEC_REG2_NNMQC_MASK;

if (norm_type > 1)
dev_dbg(xsdfec->dev, "Norm type is invalid");
norm_type = ((norm_type << XSDFEC_REG2_NORM_TYPE_LSB) &
XSDFEC_REG2_NORM_TYPE_MASK);
if (special_qc > 1)
dev_dbg(xsdfec->dev, "Special QC in invalid");
special_qc = ((special_qc << XSDFEC_REG2_SPEICAL_QC_LSB) &
XSDFEC_REG2_SPECIAL_QC_MASK);

if (no_final_parity > 1)
dev_dbg(xsdfec->dev, "No final parity check invalid");
no_final_parity =
((no_final_parity << XSDFEC_REG2_NO_FINAL_PARITY_LSB) &
XSDFEC_REG2_NO_FINAL_PARITY_MASK);
if (max_schedule &
~(XSDFEC_REG2_MAX_SCHEDULE_MASK >> XSDFEC_REG2_MAX_SCHEDULE_LSB))
dev_dbg(xsdfec->dev, "Max Schdule exceeds 2 bits");
max_schedule = ((max_schedule << XSDFEC_REG2_MAX_SCHEDULE_LSB) &
XSDFEC_REG2_MAX_SCHEDULE_MASK);

wdata = (max_schedule | no_final_parity | special_qc | norm_type |
nmqc | nlayers);

if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) {
dev_dbg(xsdfec->dev, "Writing outside of LDPC reg2 space 0x%x",
XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP));
return -EINVAL;
}
xsdfec_regwrite(xsdfec,
XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP),
wdata);
return 0;
}

static int xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off, u8 la_off,
u16 qc_off, u32 offset)
{
u32 wdata;

wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) |
(la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off);
if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) {
dev_dbg(xsdfec->dev, "Writing outside of LDPC reg3 space 0x%x",
XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP));
return -EINVAL;
}
xsdfec_regwrite(xsdfec,
XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
(offset * XSDFEC_LDPC_REG_JUMP),
wdata);
return 0;
}

static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset,
u32 *src_ptr, u32 len, const u32 base_addr,
const u32 depth)
{
u32 reg = 0;
u32 res;
u32 n, i;
u32 *addr = NULL;
struct page *page[MAX_NUM_PAGES];

/*
* Writes that go beyond the length of
* Shared Scale(SC) table should fail
*/
if ((XSDFEC_REG_WIDTH_JUMP * (offset + len)) > depth) {
dev_dbg(xsdfec->dev, "Write exceeds SC table length");
return -EINVAL;
}

n = (len * XSDFEC_REG_WIDTH_JUMP) / PAGE_SIZE;
if ((len * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)
n += 1;

res = get_user_pages_fast((unsigned long)src_ptr, n, 0, page);
if (res < n) {
for (i = 0; i < res; i++)
put_page(page[i]);
return -EINVAL;
}

for (i = 0; i < n; i++) {
addr = kmap(page[i]);
do {
xsdfec_regwrite(xsdfec,
base_addr + ((offset + reg) *
XSDFEC_REG_WIDTH_JUMP),
addr[reg]);
reg++;
} while ((reg < len) &&
((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE));
put_page(page[i]);
}
return reg;
}

static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg)
{
struct xsdfec_ldpc_params *ldpc;
int ret, n;

ldpc = kzalloc(sizeof(*ldpc), GFP_KERNEL);
if (!ldpc)
return -ENOMEM;

ret = copy_from_user(ldpc, arg, sizeof(*ldpc));
if (ret)
goto err_out;

if (xsdfec->config.code == XSDFEC_TURBO_CODE) {
ret = -EIO;
goto err_out;
}

/* Verify Device has not started */
if (xsdfec->state == XSDFEC_STARTED) {
ret = -EIO;
goto err_out;
}

if (xsdfec->config.code_wr_protect) {
ret = -EIO;
goto err_out;
}

/* Write Reg 0 */
ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize,
ldpc->code_id);
if (ret)
goto err_out;

/* Write Reg 1 */
ret = xsdfec_reg1_write(xsdfec, ldpc->psize, ldpc->no_packing, ldpc->nm,
ldpc->code_id);
if (ret)
goto err_out;

/* Write Reg 2 */
ret = xsdfec_reg2_write(xsdfec, ldpc->nlayers, ldpc->nmqc,
ldpc->norm_type, ldpc->special_qc,
ldpc->no_final_parity, ldpc->max_schedule,
ldpc->code_id);
if (ret)
goto err_out;

/* Write Reg 3 */
ret = xsdfec_reg3_write(xsdfec, ldpc->sc_off, ldpc->la_off,
ldpc->qc_off, ldpc->code_id);
if (ret)
goto err_out;

/* Write Shared Codes */
n = ldpc->nlayers / 4;
if (ldpc->nlayers % 4)
n++;

ret = xsdfec_table_write(xsdfec, ldpc->sc_off, ldpc->sc_table, n,
XSDFEC_LDPC_SC_TABLE_ADDR_BASE,
XSDFEC_SC_TABLE_DEPTH);
if (ret < 0)
goto err_out;

ret = xsdfec_table_write(xsdfec, 4 * ldpc->la_off, ldpc->la_table,
ldpc->nlayers, XSDFEC_LDPC_LA_TABLE_ADDR_BASE,
XSDFEC_LA_TABLE_DEPTH);
if (ret < 0)
goto err_out;

ret = xsdfec_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table,
ldpc->nqc, XSDFEC_LDPC_QC_TABLE_ADDR_BASE,
XSDFEC_QC_TABLE_DEPTH);
if (ret > 0)
ret = 0;
err_out:
kfree(ldpc);
return ret;
}

static u32
xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg)
{
Expand Down Expand Up @@ -366,6 +687,9 @@ static long xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd,
case XSDFEC_GET_TURBO:
rval = xsdfec_get_turbo(xsdfec, arg);
break;
case XSDFEC_ADD_LDPC_CODE_PARAMS:
rval = xsdfec_add_ldpc(xsdfec, arg);
break;
default:
/* Should not get here */
break;
Expand Down
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