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Merge branches 'pci/host-armada', 'pci/host-artpec', 'pci/host-dra7xx…
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…', 'pci/host-exynos', 'pci/host-hisi', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-qcom' and 'pci/host-spear' into next

* pci/host-armada:
  MAINTAINERS: Add maintainer for the PCIe Marvell Armada 8K driver
  PCI: armada: Reorder struct armada8k_pcie
  PCI: armada: Pass device-specific struct to internal functions
  PCI: armada: Use generic DesignWare accessors
  PCI: armada: Remove redundant struct armada8k_pcie.base
  PCI: armada: Add local base pointer
  PCI: armada: Remove unused platform data

* pci/host-artpec:
  PCI: artpec6: Add resource name comments
  PCI: artpec6: Pass device-specific struct to internal functions
  PCI: artpec6: Remove unnecessary artpec6_pcie_link_up()
  PCI: artpec6: Use generic DesignWare accessors
  PCI: artpec6: Add register accessors
  PCI: artpec6: Remove unused platform data
  PCI: artpec6: Add local struct device pointers

* pci/host-dra7xx:
  PCI: dra7xx: Reorder struct dra7xx_pcie
  PCI: dra7xx: Move struct pcie_port setup to probe function
  PCI: dra7xx: Pass device-specific struct to internal functions
  PCI: dra7xx: Use generic DesignWare accessors
  PCI: dra7xx: Set drvdata at end of probe function
  PCI: dra7xx: Remove redundant struct device pointer from dra7xx_pcie
  PCI: dra7xx: Add local struct device pointers

* pci/host-exynos:
  PCI: exynos: Reorder struct exynos_pcie
  PCI: exynos: Pass device-specific struct to internal functions
  PCI: exynos: Name private struct pointer "exynos_pcie" consistently
  PCI: exynos: Uninline register accessors
  PCI: exynos: Add local struct device pointers

* pci/host-hisi:
  PCI: hisi: Reorder struct hisi_pcie
  PCI: hisi: Pass device-specific struct to internal functions
  PCI: hisi: Include register block base in PCIE_SYS_STATE4 address
  PCI: hisi: Use generic DesignWare accessors
  PCI: hisi: Remove redundant struct hisi_pcie.reg_base
  PCI: hisi: Name private struct pointer "hisi_pcie" consistently
  PCI: hisi: Remove unused platform data
  PCI: hisi: Add local struct device pointers

* pci/host-imx6:
  PCI: imx6: Remove unused return values
  PCI: imx6: Reorder struct imx6_pcie
  PCI: imx6: Use generic DesignWare accessors
  PCI: imx6: Pass device-specific struct to internal functions
  PCI: imx6: Pass struct imx6_pcie to PHY accessors
  PCI: imx6: Removed unused struct imx6_pcie.mem_base
  PCI: imx6: Remove redundant of_node pointer
  PCI: imx6: Add local struct device pointers

* pci/host-keystone:
  PCI: keystone: Reorder struct keystone_pcie
  PCI: keystone: Add app register accessors
  PCI: keystone: Pass keystone_pcie, not va_app_base, to DBI functions
  PCI: keystone: Pass keystone_pcie, not address, to IRQ functions
  PCI: keystone: Use generic DesignWare accessors
  PCI: keystone: Add local struct device pointers

* pci/host-layerscape:
  PCI: layerscape: Reorder struct ls_pcie
  PCI: layerscape: Remove unused ls_add_pcie_port() platform_device arg
  PCI: layerscape: Move struct pcie_port setup to probe function
  PCI: layerscape: Pass device-specific struct to internal functions
  PCI: layerscape: Remove redundant struct ls_pcie.dbi
  PCI: layerscape: Remove unused platform data
  PCI: layerscape: Add local struct device pointers

* pci/host-qcom:
  PCI: qcom: Reorder struct qcom_pcie
  PCI: qcom: Remove redundant struct qcom_pcie.dev
  PCI: qcom: Remove redundant struct qcom_pcie.dbi
  PCI: qcom: Remove unused platform data

* pci/host-spear:
  PCI: spear: Clean up struct device usage
  PCI: spear: Reorder struct spear13xx_pcie
  PCI: spear: Pass device-specific struct to internal functions
  PCI: spear: Remove unused constants
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Bjorn Helgaas committed Oct 12, 2016
11 parents 22c7e1d + 3dc9d38 + 7c62efc + 8e5ec41 + 6b1f185 + f84cfdf + 9ab021b + 4841f3a + 6caaa28 + ee05369 + 6a43a42 commit 217c6d2
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Showing 13 changed files with 563 additions and 654 deletions.
8 changes: 8 additions & 0 deletions MAINTAINERS
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8936,6 +8936,14 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/versatile.txt
F: drivers/pci/host/pci-versatile.c

PCI DRIVER FOR ARMADA 8K
M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
L: linux-pci@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/pci/pci-armada8k.txt
F: drivers/pci/host/pcie-armada8k.c

PCI DRIVER FOR APPLIEDMICRO XGENE
M: Tanmay Inamdar <tinamdar@apm.com>
L: linux-pci@vger.kernel.org
Expand Down
103 changes: 45 additions & 58 deletions drivers/pci/host/pci-dra7xx.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,11 +64,10 @@
#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF

struct dra7xx_pcie {
void __iomem *base;
struct phy **phy;
int phy_count;
struct device *dev;
struct pcie_port pp;
void __iomem *base; /* DT ti_conf */
int phy_count; /* DT phy-names count */
struct phy **phy;
};

#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
Expand All @@ -84,17 +83,6 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
writel(value, pcie->base + offset);
}

static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
{
return readl(pp->dbi_base + offset);
}

static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
u32 value)
{
writel(value, pp->dbi_base + offset);
}

static int dra7xx_pcie_link_up(struct pcie_port *pp)
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
Expand All @@ -103,13 +91,14 @@ static int dra7xx_pcie_link_up(struct pcie_port *pp)
return !!(reg & LINK_UP);
}

static int dra7xx_pcie_establish_link(struct pcie_port *pp)
static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
struct pcie_port *pp = &dra7xx->pp;
struct device *dev = pp->dev;
u32 reg;

if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "link is already up\n");
dev_err(dev, "link is already up\n");
return 0;
}

Expand All @@ -120,10 +109,8 @@ static int dra7xx_pcie_establish_link(struct pcie_port *pp)
return dw_pcie_wait_for_link(pp);
}

static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);

dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
~INTERRUPTS);
dra7xx_pcie_writel(dra7xx,
Expand All @@ -142,17 +129,19 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)

static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);

pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;

dw_pcie_setup_rc(pp);

dra7xx_pcie_establish_link(pp);
dra7xx_pcie_establish_link(dra7xx);
if (IS_ENABLED(CONFIG_PCI_MSI))
dw_pcie_msi_init(pp);
dra7xx_pcie_enable_interrupts(pp);
dra7xx_pcie_enable_interrupts(dra7xx);
}

static struct pcie_host_ops dra7xx_pcie_host_ops = {
Expand Down Expand Up @@ -196,8 +185,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)

static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
{
struct pcie_port *pp = arg;
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
struct dra7xx_pcie *dra7xx = arg;
struct pcie_port *pp = &dra7xx->pp;
u32 reg;

reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
Expand All @@ -223,51 +212,51 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
{
struct dra7xx_pcie *dra7xx = arg;
struct device *dev = dra7xx->pp.dev;
u32 reg;

reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);

if (reg & ERR_SYS)
dev_dbg(dra7xx->dev, "System Error\n");
dev_dbg(dev, "System Error\n");

if (reg & ERR_FATAL)
dev_dbg(dra7xx->dev, "Fatal Error\n");
dev_dbg(dev, "Fatal Error\n");

if (reg & ERR_NONFATAL)
dev_dbg(dra7xx->dev, "Non Fatal Error\n");
dev_dbg(dev, "Non Fatal Error\n");

if (reg & ERR_COR)
dev_dbg(dra7xx->dev, "Correctable Error\n");
dev_dbg(dev, "Correctable Error\n");

if (reg & ERR_AXI)
dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n");
dev_dbg(dev, "AXI tag lookup fatal Error\n");

if (reg & ERR_ECRC)
dev_dbg(dra7xx->dev, "ECRC Error\n");
dev_dbg(dev, "ECRC Error\n");

if (reg & PME_TURN_OFF)
dev_dbg(dra7xx->dev,
dev_dbg(dev,
"Power Management Event Turn-Off message received\n");

if (reg & PME_TO_ACK)
dev_dbg(dra7xx->dev,
dev_dbg(dev,
"Power Management Turn-Off Ack message received\n");

if (reg & PM_PME)
dev_dbg(dra7xx->dev,
"PM Power Management Event message received\n");
dev_dbg(dev, "PM Power Management Event message received\n");

if (reg & LINK_REQ_RST)
dev_dbg(dra7xx->dev, "Link Request Reset\n");
dev_dbg(dev, "Link Request Reset\n");

if (reg & LINK_UP_EVT)
dev_dbg(dra7xx->dev, "Link-up state change\n");
dev_dbg(dev, "Link-up state change\n");

if (reg & CFG_BME_EVT)
dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n");
dev_dbg(dev, "CFG 'Bus Master Enable' change\n");

if (reg & CFG_MSE_EVT)
dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n");
dev_dbg(dev, "CFG 'Memory Space Enable' change\n");

dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);

Expand All @@ -278,26 +267,21 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
struct platform_device *pdev)
{
int ret;
struct pcie_port *pp;
struct pcie_port *pp = &dra7xx->pp;
struct device *dev = pp->dev;
struct resource *res;
struct device *dev = &pdev->dev;

pp = &dra7xx->pp;
pp->dev = dev;
pp->ops = &dra7xx_pcie_host_ops;

pp->irq = platform_get_irq(pdev, 1);
if (pp->irq < 0) {
dev_err(dev, "missing IRQ resource\n");
return -EINVAL;
}

ret = devm_request_irq(&pdev->dev, pp->irq,
dra7xx_pcie_msi_irq_handler,
ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
IRQF_SHARED | IRQF_NO_THREAD,
"dra7-pcie-msi", pp);
"dra7-pcie-msi", dra7xx);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
dev_err(dev, "failed to request irq\n");
return ret;
}

Expand All @@ -314,7 +298,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,

ret = dw_pcie_host_init(pp);
if (ret) {
dev_err(dra7xx->dev, "failed to initialize host\n");
dev_err(dev, "failed to initialize host\n");
return ret;
}

Expand All @@ -332,6 +316,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
void __iomem *base;
struct resource *res;
struct dra7xx_pcie *dra7xx;
struct pcie_port *pp;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
char name[10];
Expand All @@ -343,6 +328,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
if (!dra7xx)
return -ENOMEM;

pp = &dra7xx->pp;
pp->dev = dev;
pp->ops = &dra7xx_pcie_host_ops;

irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(dev, "missing IRQ resource\n");
Expand Down Expand Up @@ -390,7 +379,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)

dra7xx->base = base;
dra7xx->phy = phy;
dra7xx->dev = dev;
dra7xx->phy_count = phy_count;

pm_runtime_enable(dev);
Expand All @@ -407,7 +395,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,
"pcie_reset");
if (ret) {
dev_err(&pdev->dev, "gpio%d request failed, ret %d\n",
dev_err(dev, "gpio%d request failed, ret %d\n",
gpio_sel, ret);
goto err_gpio;
}
Expand All @@ -420,12 +408,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
reg &= ~LTSSM_EN;
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);

platform_set_drvdata(pdev, dra7xx);

ret = dra7xx_add_pcie_port(dra7xx, pdev);
if (ret < 0)
goto err_gpio;

platform_set_drvdata(pdev, dra7xx);
return 0;

err_gpio:
Expand All @@ -451,9 +438,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
u32 val;

/* clear MSE */
val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
val = dw_pcie_readl_rc(pp, PCI_COMMAND);
val &= ~PCI_COMMAND_MEMORY;
dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
dw_pcie_writel_rc(pp, PCI_COMMAND, val);

return 0;
}
Expand All @@ -465,9 +452,9 @@ static int dra7xx_pcie_resume(struct device *dev)
u32 val;

/* set MSE */
val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
val = dw_pcie_readl_rc(pp, PCI_COMMAND);
val |= PCI_COMMAND_MEMORY;
dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
dw_pcie_writel_rc(pp, PCI_COMMAND, val);

return 0;
}
Expand Down
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