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drm: sun4i: Add DT bindings documentation
The display pipeline of the Allwinner A10 is involving several loosely coupled components. Add a documentation for the bindings. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
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| Allwinner A10 Display Pipeline | ||
| ============================== | ||
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| The Allwinner A10 Display pipeline is composed of several components | ||
| that are going to be documented below: | ||
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| TV Encoder | ||
| ---------- | ||
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| The TV Encoder supports the composite and VGA output. It is one end of | ||
| the pipeline. | ||
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| Required properties: | ||
| - compatible: value should be "allwinner,sun4i-a10-tv-encoder". | ||
| - reg: base address and size of memory-mapped region | ||
| - clocks: the clocks driving the TV encoder | ||
| - resets: phandle to the reset controller driving the encoder | ||
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| - ports: A ports node with endpoint definitions as defined in | ||
| Documentation/devicetree/bindings/media/video-interfaces.txt. The | ||
| first port should be the input endpoint. | ||
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| TCON | ||
| ---- | ||
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| The TCON acts as a timing controller for RGB, LVDS and TV interfaces. | ||
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| Required properties: | ||
| - compatible: value should be "allwinner,sun5i-a13-tcon". | ||
| - reg: base address and size of memory-mapped region | ||
| - interrupts: interrupt associated to this IP | ||
| - clocks: phandles to the clocks feeding the TCON. Three are needed: | ||
| - 'ahb': the interface clocks | ||
| - 'tcon-ch0': The clock driving the TCON channel 0 | ||
| - 'tcon-ch1': The clock driving the TCON channel 1 | ||
| - resets: phandles to the reset controllers driving the encoder | ||
| - "lcd": the reset line for the TCON channel 0 | ||
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| - clock-names: the clock names mentioned above | ||
| - reset-names: the reset names mentioned above | ||
| - clock-output-names: Name of the pixel clock created | ||
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| - ports: A ports node with endpoint definitions as defined in | ||
| Documentation/devicetree/bindings/media/video-interfaces.txt. The | ||
| first port should be the input endpoint, the second one the output | ||
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| The output should have two endpoints. The first is the block | ||
| connected to the TCON channel 0 (usually a panel or a bridge), the | ||
| second the block connected to the TCON channel 1 (usually the TV | ||
| encoder) | ||
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| Display Engine Backend | ||
| ---------------------- | ||
|
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| The display engine backend exposes layers and sprites to the | ||
| system. | ||
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| Required properties: | ||
| - compatible: value must be one of: | ||
| * allwinner,sun5i-a13-display-backend | ||
| - reg: base address and size of the memory-mapped region. | ||
| - clocks: phandles to the clocks feeding the frontend and backend | ||
| * ahb: the backend interface clock | ||
| * mod: the backend module clock | ||
| * ram: the backend DRAM clock | ||
| - clock-names: the clock names mentioned above | ||
| - resets: phandles to the reset controllers driving the backend | ||
|
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| - ports: A ports node with endpoint definitions as defined in | ||
| Documentation/devicetree/bindings/media/video-interfaces.txt. The | ||
| first port should be the input endpoints, the second one the output | ||
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| Display Engine Frontend | ||
| ----------------------- | ||
|
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| The display engine frontend does formats conversion, scaling, | ||
| deinterlacing and color space conversion. | ||
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| Required properties: | ||
| - compatible: value must be one of: | ||
| * allwinner,sun5i-a13-display-frontend | ||
| - reg: base address and size of the memory-mapped region. | ||
| - interrupts: interrupt associated to this IP | ||
| - clocks: phandles to the clocks feeding the frontend and backend | ||
| * ahb: the backend interface clock | ||
| * mod: the backend module clock | ||
| * ram: the backend DRAM clock | ||
| - clock-names: the clock names mentioned above | ||
| - resets: phandles to the reset controllers driving the backend | ||
|
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||
| - ports: A ports node with endpoint definitions as defined in | ||
| Documentation/devicetree/bindings/media/video-interfaces.txt. The | ||
| first port should be the input endpoints, the second one the outputs | ||
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| Display Engine Pipeline | ||
| ----------------------- | ||
|
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| The display engine pipeline (and its entry point, since it can be | ||
| either directly the backend or the frontend) is represented as an | ||
| extra node. | ||
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| Required properties: | ||
| - compatible: value must be one of: | ||
| * allwinner,sun5i-a13-display-engine | ||
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| - allwinner,pipelines: list of phandle to the display engine | ||
| frontends available. | ||
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| Example: | ||
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| panel: panel { | ||
| compatible = "olimex,lcd-olinuxino-43-ts"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| port { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| panel_input: endpoint { | ||
| remote-endpoint = <&tcon0_out_panel>; | ||
| }; | ||
| }; | ||
| }; | ||
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| tve0: tv-encoder@01c0a000 { | ||
| compatible = "allwinner,sun4i-a10-tv-encoder"; | ||
| reg = <0x01c0a000 0x1000>; | ||
| clocks = <&ahb_gates 34>; | ||
| resets = <&tcon_ch0_clk 0>; | ||
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| port { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| tve0_in_tcon0: endpoint@0 { | ||
| reg = <0>; | ||
| remote-endpoint = <&tcon0_out_tve0>; | ||
| }; | ||
| }; | ||
| }; | ||
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| tcon0: lcd-controller@1c0c000 { | ||
| compatible = "allwinner,sun5i-a13-tcon"; | ||
| reg = <0x01c0c000 0x1000>; | ||
| interrupts = <44>; | ||
| resets = <&tcon_ch0_clk 1>; | ||
| reset-names = "lcd"; | ||
| clocks = <&ahb_gates 36>, | ||
| <&tcon_ch0_clk>, | ||
| <&tcon_ch1_clk>; | ||
| clock-names = "ahb", | ||
| "tcon-ch0", | ||
| "tcon-ch1"; | ||
| clock-output-names = "tcon-pixel-clock"; | ||
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| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| tcon0_in: port@0 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| reg = <0>; | ||
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| tcon0_in_be0: endpoint@0 { | ||
| reg = <0>; | ||
| remote-endpoint = <&be0_out_tcon0>; | ||
| }; | ||
| }; | ||
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| tcon0_out: port@1 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| reg = <1>; | ||
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| tcon0_out_panel: endpoint@0 { | ||
| reg = <0>; | ||
| remote-endpoint = <&panel_input>; | ||
| }; | ||
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| tcon0_out_tve0: endpoint@1 { | ||
| reg = <1>; | ||
| remote-endpoint = <&tve0_in_tcon0>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; | ||
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| fe0: display-frontend@1e00000 { | ||
| compatible = "allwinner,sun5i-a13-display-frontend"; | ||
| reg = <0x01e00000 0x20000>; | ||
| interrupts = <47>; | ||
| clocks = <&ahb_gates 46>, <&de_fe_clk>, | ||
| <&dram_gates 25>; | ||
| clock-names = "ahb", "mod", | ||
| "ram"; | ||
| resets = <&de_fe_clk>; | ||
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| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| fe0_out: port@1 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| reg = <1>; | ||
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| fe0_out_be0: endpoint { | ||
| remote-endpoint = <&be0_in_fe0>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; | ||
|
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| be0: display-backend@1e60000 { | ||
| compatible = "allwinner,sun5i-a13-display-backend"; | ||
| reg = <0x01e60000 0x10000>; | ||
| clocks = <&ahb_gates 44>, <&de_be_clk>, | ||
| <&dram_gates 26>; | ||
| clock-names = "ahb", "mod", | ||
| "ram"; | ||
| resets = <&de_be_clk>; | ||
|
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| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| be0_in: port@0 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| reg = <0>; | ||
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| be0_in_fe0: endpoint@0 { | ||
| reg = <0>; | ||
| remote-endpoint = <&fe0_out_be0>; | ||
| }; | ||
| }; | ||
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| be0_out: port@1 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| reg = <1>; | ||
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| be0_out_tcon0: endpoint@0 { | ||
| reg = <0>; | ||
| remote-endpoint = <&tcon0_in_be0>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; | ||
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| display-engine { | ||
| compatible = "allwinner,sun5i-a13-display-engine"; | ||
| allwinner,pipelines = <&fe0>; | ||
| }; |