[ARM] nommu: provide a way for correct control register value selection

Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
mariux64 · Jun 29, 2006 · 22b1908 · 22b1908
1 parent 264edb3
commit 22b1908
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Showing 15 changed files with 101 additions and 125 deletions.
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
@@ -440,11 +440,12 @@ __arm1020_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
 #endif
+
+	adr	r5, arm1020_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm1020_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm1020_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
 #endif
@@ -456,12 +457,9 @@ __arm1020_setup:
 	 * .RVI ZFRS BLDP WCAM
 	 * .011 1001 ..11 0101
 	 */
-	.type	arm1020_cr1_clear, #object
-	.type	arm1020_cr1_set, #object
-arm1020_cr1_clear:
-	.word	0x593f
-arm1020_cr1_set:
-	.word	0x3935
+	.type	arm1020_crval, #object
+arm1020_crval:
+	crval	clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
@@ -422,11 +422,11 @@ __arm1020e_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
 #endif
+	adr	r5, arm1020e_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm1020e_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm1020e_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
 #endif
@@ -438,12 +438,9 @@ __arm1020e_setup:
 	 * .RVI ZFRS BLDP WCAM
 	 * .011 1001 ..11 0101
 	 */
-	.type	arm1020e_cr1_clear, #object
-	.type	arm1020e_cr1_set, #object
-arm1020e_cr1_clear:
-	.word	0x5f3f
-arm1020e_cr1_set:
-	.word	0x3935
+	.type	arm1020e_crval, #object
+arm1020e_crval:
+	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
@@ -404,11 +404,11 @@ __arm1022_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
 #endif
+	adr	r5, arm1022_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm1022_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm1022_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 	orr	r0, r0, #0x4000 		@ .R..............
 #endif
@@ -421,12 +421,9 @@ __arm1022_setup:
 	 * .011 1001 ..11 0101
 	 * 
 	 */
-	.type	arm1022_cr1_clear, #object
-	.type	arm1022_cr1_set, #object
-arm1022_cr1_clear:
-	.word	0x7f3f
-arm1022_cr1_set:
-	.word	0x3935
+	.type	arm1022_crval, #object
+arm1022_crval:
+	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
@@ -399,11 +399,11 @@ __arm1026_setup:
 	mov	r0, #4				@ explicitly disable writeback
 	mcr	p15, 7, r0, c15, c0, 0
 #endif
+	adr	r5, arm1026_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm1026_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm1026_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
 #endif
@@ -416,12 +416,9 @@ __arm1026_setup:
 	 * .011 1001 ..11 0101
 	 * 
 	 */
-	.type	arm1026_cr1_clear, #object
-	.type	arm1026_cr1_set, #object
-arm1026_cr1_clear:
-	.word	0x7f3f
-arm1026_cr1_set:
-	.word	0x3935
+	.type	arm1026_crval, #object
+arm1026_crval:
+	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
@@ -169,11 +169,11 @@ __arm720_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
 #endif
+	adr	r5, arm720_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register
-	ldr	r5, arm720_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm720_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 	mov	pc, lr				@ __ret (head.S)
 	.size	__arm720_setup, . - __arm720_setup
 
@@ -183,12 +183,9 @@ __arm720_setup:
 	 * ..1. 1001 ..11 1101
 	 * 
 	 */
-	.type	arm720_cr1_clear, #object
-	.type	arm720_cr1_set, #object
-arm720_cr1_clear:
-	.word	0x2f3f
-arm720_cr1_set:
-	.word	0x213d
+	.type	arm720_crval, #object
+arm720_crval:
+	crval	clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
 
 		__INITDATA
 

diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
@@ -391,11 +391,11 @@ __arm920_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
 #endif
+	adr	r5, arm920_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm920_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm920_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 	mov	pc, lr
 	.size	__arm920_setup, . - __arm920_setup
 
@@ -405,12 +405,9 @@ __arm920_setup:
 	 * ..11 0001 ..11 0101
 	 * 
 	 */
-	.type	arm920_cr1_clear, #object
-	.type	arm920_cr1_set, #object
-arm920_cr1_clear:
-	.word	0x3f3f
-arm920_cr1_set:
-	.word	0x3135
+	.type	arm920_crval, #object
+arm920_crval:
+	crval	clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
@@ -395,11 +395,11 @@ __arm922_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
 #endif
+	adr	r5, arm922_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm922_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm922_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 	mov	pc, lr
 	.size	__arm922_setup, . - __arm922_setup
 
@@ -409,12 +409,9 @@ __arm922_setup:
 	 * ..11 0001 ..11 0101
 	 * 
 	 */
-	.type	arm922_cr1_clear, #object
-	.type	arm922_cr1_set, #object
-arm922_cr1_clear:
-	.word	0x3f3f
-arm922_cr1_set:
-	.word	0x3135
+	.type	arm922_crval, #object
+arm922_crval:
+	crval	clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
@@ -455,11 +455,10 @@ __arm925_setup:
 	mcr	p15, 7, r0, c15, c0, 0
 #endif
 
+	adr	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm925_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm925_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 	orr	r0, r0, #0x4000			@ .1.. .... .... ....
 #endif
@@ -472,12 +471,9 @@ __arm925_setup:
 	 * .011 0001 ..11 1101
 	 * 
 	 */
-	.type	arm925_cr1_clear, #object
-	.type	arm925_cr1_set, #object
-arm925_cr1_clear:
-	.word	0x7f3f
-arm925_cr1_set:
-	.word	0x313d
+	.type	arm925_crval, #object
+arm925_crval:
+	crval	clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
@@ -404,11 +404,11 @@ __arm926_setup:
 	mcr	p15, 7, r0, c15, c0, 0
 #endif 
 
+	adr	r5, arm926_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, arm926_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, arm926_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 	orr	r0, r0, #0x4000			@ .1.. .... .... ....
 #endif
@@ -421,12 +421,9 @@ __arm926_setup:
 	 * .011 0001 ..11 0101
 	 * 
 	 */
-	.type	arm926_cr1_clear, #object
-	.type	arm926_cr1_set, #object
-arm926_cr1_clear:
-	.word	0x7f3f
-arm926_cr1_set:
-	.word	0x3135
+	.type	arm926_crval, #object
+arm926_crval:
+	crval	clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
@@ -49,3 +49,13 @@
 	.macro	asid, rd, rn
 	and	\rd, \rn, #255
 	.endm
+
+	.macro	crval, clear, mmuset, ucset
+#ifdef CONFIG_MMU
+	.word	\clear
+	.word	\mmuset
+#else
+	.word	\clear
+	.word	\ucset
+#endif
+	.endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
@@ -185,11 +185,12 @@ __sa110_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
 #endif
+
+	adr	r5, sa110_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, sa110_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, sa110_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 	mov	pc, lr
 	.size	__sa110_setup, . - __sa110_setup
 
@@ -199,12 +200,9 @@ __sa110_setup:
 	 * ..01 0001 ..11 1101
 	 * 
 	 */
-	.type	sa110_cr1_clear, #object
-	.type	sa110_cr1_set, #object
-sa110_cr1_clear:
-	.word	0x3f3f
-sa110_cr1_set:
-	.word	0x113d
+	.type	sa110_crval, #object
+sa110_crval:
+	crval	clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
@@ -198,11 +198,11 @@ __sa1100_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
 #endif
+	adr	r5, sa1100_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
-	ldr	r5, sa1100_cr1_clear
 	bic	r0, r0, r5
-	ldr	r5, sa1100_cr1_set
-	orr	r0, r0, r5
+	orr	r0, r0, r6
 	mov	pc, lr
 	.size	__sa1100_setup, . - __sa1100_setup
 
@@ -212,12 +212,9 @@ __sa1100_setup:
 	 * ..11 0001 ..11 1101
 	 * 
 	 */
-	.type	sa1100_cr1_clear, #object
-	.type	sa1100_cr1_set, #object
-sa1100_cr1_clear:
-	.word	0x3f3f
-sa1100_cr1_set:
-	.word	0x313d
+	.type	sa1100_crval, #object
+sa1100_crval:
+	crval	clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
 
 	__INITDATA
 

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
@@ -212,11 +212,11 @@ __v6_setup:
 	orr	r0, r0, #(0xf << 20)
 	mcr	p15, 0, r0, c1, c0, 2		@ Enable full access to VFP
 #endif
+	adr	r5, v6_crval
+	ldmia	r5, {r5, r6}
 	mrc	p15, 0, r0, c1, c0, 0		@ read control register
-	ldr	r5, v6_cr1_clear		@ get mask for bits to clear
 	bic	r0, r0, r5			@ clear bits them
-	ldr	r5, v6_cr1_set			@ get mask for bits to set
-	orr	r0, r0, r5			@ set them
+	orr	r0, r0, r6			@ set them
 	mov	pc, lr				@ return to head.S:__ret
 
 	/*
@@ -225,12 +225,9 @@ __v6_setup:
 	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 	 *         0 110       0011 1.00 .111 1101 < we want
 	 */
-	.type	v6_cr1_clear, #object
-	.type	v6_cr1_set, #object
-v6_cr1_clear:
-	.word	0x01e0fb7f
-v6_cr1_set:
-	.word	0x00c0387d
+	.type	v6_crval, #object
+v6_crval:
+	crval	clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 
 	.type	v6_processor_functions, #object
 ENTRY(v6_processor_functions)