Skip to content

Commit

Permalink
Merge tag 'kvm-ppc-fixes-5.2-1' of git://git.kernel.org/pub/scm/linux…
Browse files Browse the repository at this point in the history 
…/kernel/git/paulus/powerpc into kvm-master

PPC KVM fixes for 5.2

- Several bug fixes for the new XIVE-native code.
- Replace kvm->lock by other mutexes in several places where we hold a
  vcpu mutex, to avoid lock order inversions.
- Fix a lockdep warning on guest entry for radix-mode guests.
- Fix a bug causing user-visible corruption of SPRG3 on the host.
  • Loading branch information
Paolo Bonzini committed May 31, 2019
2 parents 66f61c9 + d724c9e commit 24e8a2c
Show file tree
Hide file tree
Showing 5,267 changed files with 7,897 additions and 25,677 deletions.
The diff you're trying to view is too large. We only load the first 3000 changed files.
9 changes: 5 additions & 4 deletions Documentation/arm64/silicon-errata.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,13 +58,14 @@ stable kernels.
| ARM | Cortex-A72 | #853709 | N/A |
| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
| ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 |
| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
| ARM | Neoverse-N1 | #1188873 | ARM64_ERRATUM_1188873 |
| ARM | MMU-500 | #841119,#826419 | N/A |
| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
| ARM | MMU-500 | #841119,826419 | N/A |
| | | | |
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
Expand Down
2 changes: 1 addition & 1 deletion Documentation/bpf/btf.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,7 @@ The following sections detail encoding of each kind.
``btf_type`` is followed by a ``u32`` with the following bits arrangement::

#define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24)
#define BTF_INT_OFFSET(VAL) (((VAL & 0x00ff0000)) >> 16)
#define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16)
#define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff)

The ``BTF_INT_ENCODING`` has the following attributes::
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)

quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \
cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
$(DT_EXTRACT_EX) $< > $@

$(obj)/%.example.dts: $(src)/%.yaml FORCE
Expand Down
4 changes: 2 additions & 2 deletions Documentation/devicetree/bindings/arm/arm-boards
View file
Original file line number Diff line number Diff line change
Expand Up @@ -216,7 +216,7 @@ Example:
#size-cells = <0>;

A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -225,7 +225,7 @@ Example:
.....

A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
Expand Down
12 changes: 6 additions & 6 deletions Documentation/devicetree/bindings/arm/cpu-capacity.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,7 @@ cpus {
};

A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -129,7 +129,7 @@ cpus {
};

A57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -140,7 +140,7 @@ cpus {
};

A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -151,7 +151,7 @@ cpus {
};

A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -162,7 +162,7 @@ cpus {
};

A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -173,7 +173,7 @@ cpus {
};

A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/arm/omap/crossbar.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ Examples:
Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
further details.

An interrupt consumer on an SoC using crossbar will use:
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks.

[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml

Example: Clock controller node:

Expand Down
24 changes: 13 additions & 11 deletions Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -92,6 +92,8 @@ properties:
minItems: 2
maxItems: 4

ranges: true

interrupts:
description: Interrupt source of the parent interrupt controller on
secondary GICs, or VGIC maintenance interrupt on primary GIC (see
Expand Down Expand Up @@ -197,28 +199,28 @@ examples:
interrupt-controller@e1101000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
interrupts = <1 8 0xf04>;
ranges = <0 0 0 0xe1100000 0 0x100000>;
reg = <0x0 0xe1110000 0 0x01000>,
<0x0 0xe112f000 0 0x02000>,
<0x0 0xe1140000 0 0x10000>,
<0x0 0xe1160000 0 0x10000>;
ranges = <0 0xe1100000 0x100000>;
reg = <0xe1110000 0x01000>,
<0xe112f000 0x02000>,
<0xe1140000 0x10000>,
<0xe1160000 0x10000>;
v2m0: v2m@8000 {
v2m0: v2m@80000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x80000 0 0x1000>;
reg = <0x80000 0x1000>;
};
//...
v2mN: v2m@9000 {
v2mN: v2m@90000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x90000 0 0x1000>;
reg = <0x90000 0x1000>;
};
};
...
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ Required properties:
- marvell,spi-base : List of GIC base SPI interrupts, one for each
ODMI frame. Those SPI interrupts are 0-based,
i.e marvell,spi-base = <128> will use SPI #96.
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
for details about the GIC Device Tree binding.

Example:
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ Optional properties:
- power-supply: specifies the power source. It can either be a regulator
or a gpio which enables a regulator, i.e. a regulator-fixed as
described in
Documentation/devicetree/bindings/regulator/fixed-regulator.txt
Documentation/devicetree/bindings/regulator/fixed-regulator.yaml

Example:

Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ Optional children nodes:
Children nodes represent the available nand chips.

Other properties:
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.

Example demonstrate on AXG SoC:

Expand Down
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,12 +101,12 @@ Required properties:
number (e.g., 0, 1, 2, etc.)
- #address-cells : see partition.txt
- #size-cells : see partition.txt
- nand-ecc-strength : see nand.txt
- nand-ecc-step-size : must be 512 or 1024. See nand.txt
- nand-ecc-strength : see nand-controller.yaml
- nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml

Optional properties:
- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
chip-select. See nand.txt
chip-select. See nand-controller.yaml
- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
expected for the ECC layout in use. This size, in
addition to the strength and step-size,
Expand Down
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/denali-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,16 +22,16 @@ Sub-nodes:
select is connected.

Optional properties:
- nand-ecc-step-size: see nand.txt for details.
- nand-ecc-step-size: see nand-controller.yaml for details.
If present, the value must be
512 for "altr,socfpga-denali-nand"
1024 for "socionext,uniphier-denali-nand-v5a"
1024 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-strength: see nand.txt for details. Valid values are:
- nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
8, 16 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-maximize: see nand.txt for details
- nand-ecc-maximize: see nand-controller.yaml for details

The chip nodes may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
Expand Down
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/fsmc-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,9 @@ Optional properties:
command is asserted. Zero means one cycle, 255 means 256
cycles.
- bank: default NAND bank to use (0-3 are valid, 0 is the default).
- nand-ecc-mode : see nand.txt
- nand-ecc-strength : see nand.txt
- nand-ecc-step-size : see nand.txt
- nand-ecc-mode : see nand-controller.yaml
- nand-ecc-strength : see nand-controller.yaml
- nand-ecc-step-size : see nand-controller.yaml

Can support 1-bit HW ECC (default) or if stronger correction is required,
software-based BCH.
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/mtd/gpmc-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

For NAND specific properties such as ECC modes or bus width, please refer to
Documentation/devicetree/bindings/mtd/nand.txt
Documentation/devicetree/bindings/mtd/nand-controller.yaml


Required properties:
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/mtd/hisi504-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ Required properties:
NAND controller's registers. The second contains base
physical address and size of NAND controller's buffer.
- interrupts: Interrupt number for nfc.
- nand-bus-width: See nand.txt.
- nand-bus-width: See nand-controller.yaml.
- nand-ecc-mode: Support none and hw ecc mode.
- #address-cells: Partition address, should be set 1.
- #size-cells: Partition size, should be set 1.
Expand Down
14 changes: 7 additions & 7 deletions Documentation/devicetree/bindings/mtd/marvell-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,29 +36,29 @@ Children nodes represent the available NAND chips.

Required properties:
- reg: shall contain the native Chip Select ids (0-3).
- nand-rb: see nand.txt (0-1).
- nand-rb: see nand-controller.yaml (0-1).

Optional properties:
- marvell,nand-keep-config: orders the driver not to take the timings
from the core and leaving them completely untouched. Bootloader
timings will then be used.
- label: MTD name.
- nand-on-flash-bbt: see nand.txt.
- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
- nand-ecc-algo: see nand.txt. This property is essentially useful when
- nand-on-flash-bbt: see nand-controller.yaml.
- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
not using hardware ECC. Howerver, it may be added when using hardware
ECC for clarification but will be ignored by the driver because ECC
mode is chosen depending on the page size and the strength required by
the NAND chip. This value may be overwritten with nand-ecc-strength
property.
- nand-ecc-strength: see nand.txt.
- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
- nand-ecc-strength: see nand-controller.yaml.
- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
step size will shrink or grow in order to fit the required strength.
Step sizes are not completely random for all and follow certain
patterns described in AN-379, "Marvell SoC NFC ECC".

See Documentation/devicetree/bindings/mtd/nand.txt for more details on
See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
generic bindings.


Expand Down
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/mxc-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@ Required properties:
- compatible: "fsl,imxXX-nand"
- reg: address range of the nfc block
- interrupts: irq to be used
- nand-bus-width: see nand.txt
- nand-ecc-mode: see nand.txt
- nand-on-flash-bbt: see nand.txt
- nand-bus-width: see nand-controller.yaml
- nand-ecc-mode: see nand-controller.yaml
- nand-on-flash-bbt: see nand-controller.yaml

Example:

Expand Down
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,14 +26,14 @@ Optional children node properties:
"hw" is supported.
- nand-ecc-algo: string, algorithm of NAND ECC.
Supported values with "hw" ECC mode are: "rs", "bch".
- nand-bus-width : See nand.txt
- nand-on-flash-bbt: See nand.txt
- nand-bus-width : See nand-controller.yaml
- nand-on-flash-bbt: See nand-controller.yaml
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step (always 512). Supported strength using HW ECC
modes are:
- RS: 4, 6, 8
- BCH: 4, 8, 14, 16
- nand-ecc-maximize: See nand.txt
- nand-ecc-maximize: See nand-controller.yaml
- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
are chosen.
- wp-gpios: GPIO specifier for the write protect pin.
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/mtd/oxnas-nand.txt
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
* Oxford Semiconductor OXNAS NAND Controller

Please refer to nand.txt for generic information regarding MTD NAND bindings.
Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.

Required properties:
- compatible: "oxsemi,ox820-nand"
Expand Down
4 changes: 2 additions & 2 deletions Documentation/devicetree/bindings/mtd/qcom_nandc.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,8 +47,8 @@ Required properties:
- #size-cells: see partition.txt

Optional properties:
- nand-bus-width: see nand.txt
- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will
- nand-bus-width: see nand-controller.yaml
- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
be used according to chip requirement and available
OOB size.

Expand Down
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,16 +6,16 @@ Required properties:
"samsung,s3c2412-nand"
"samsung,s3c2440-nand"
- reg : register's location and length.
- #address-cells, #size-cells : see nand.txt
- #address-cells, #size-cells : see nand-controller.yaml
- clocks : phandle to the nand controller clock
- clock-names : must contain "nand"

Optional child nodes:
Child nodes representing the available nand chips.

Optional child properties:
- nand-ecc-mode : see nand.txt
- nand-on-flash-bbt : see nand.txt
- nand-ecc-mode : see nand-controller.yaml
- nand-on-flash-bbt : see nand-controller.yaml

Each child device node may optionally contain a 'partitions' sub-node,
which further contains sub-nodes describing the flash partition mapping.
Expand Down
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,9 @@ Required properties:
- reg: describes the CS lines assigned to the NAND device.

Optional properties:
- nand-on-flash-bbt: see nand.txt
- nand-ecc-strength: see nand.txt
- nand-ecc-step-size: see nand.txt
- nand-on-flash-bbt: see nand-controller.yaml
- nand-ecc-strength: see nand-controller.yaml
- nand-ecc-step-size: see nand-controller.yaml

The following ECC strength and step size are currently supported:
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/mtd/tango-nand.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ Required properties:
- #size-cells: <0>

Children nodes represent the available NAND chips.
See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.

Example:

Expand Down
Loading

0 comments on commit 24e8a2c

Please sign in to comment.