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Merge branch 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm
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* 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] nommu: backtrace code must not reference a discarded section
  [ARM] nommu: Initial uCLinux support for MMU-based CPUs
  [ARM] nommu: prevent Xscale-based machines being selected
  [ARM] nommu: export flush_dcache_page()
  [ARM] nommu: remove fault-armv, mmap and mm-armv files from nommu build
  [ARM] Remove TABLE_SIZE, and several unused function prototypes
  [ARM] nommu: Provide a simple flush_dcache_page implementation
  [ARM] nommu: add arch/arm/Kconfig-nommu to Kconfig files
  [ARM] nommu: add stubs for ioremap and friends
  [ARM] nommu: avoid selecting TLB and CPU specific copy code
  [ARM] nommu: uaccess tweaks
  [ARM] nommu: adjust headers for !MMU ARM systems
  [ARM] nommu: we need the TLS register emulation for nommu mode
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Linus Torvalds committed Jun 28, 2006
2 parents 76a2227 + 583e7f5 commit 27d68a3
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Showing 37 changed files with 675 additions and 172 deletions.
9 changes: 9 additions & 0 deletions arch/arm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -188,23 +188,27 @@ config ARCH_IMX

config ARCH_IOP3XX
bool "IOP3xx-based"
depends on MMU
select PCI
help
Support for Intel's IOP3XX (XScale) family of processors.

config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
help
Support for Intel's IXP4XX (XScale) family of processors.

config ARCH_IXP2000
bool "IXP2400/2800-based"
depends on MMU
select PCI
help
Support for Intel's IXP2400/2800 (XScale) family of processors.

config ARCH_IXP23XX
bool "IXP23XX-based"
depends on MMU
select PCI
help
Support for Intel's IXP23xx (XScale) family of processors.
Expand All @@ -229,6 +233,7 @@ config ARCH_PNX4008

config ARCH_PXA
bool "PXA2xx-based"
depends on MMU
select ARCH_MTD_XIP
help
Support for Intel's PXA2XX processor line.
Expand Down Expand Up @@ -339,6 +344,10 @@ config XSCALE_PMU
depends on CPU_XSCALE && !XSCALE_PMU_TIMER
default y

if !MMU
source "arch/arm/Kconfig-nommu"
endif

endmenu

source "arch/arm/common/Kconfig"
Expand Down
7 changes: 5 additions & 2 deletions arch/arm/kernel/armksyms.c
Original file line number Diff line number Diff line change
Expand Up @@ -109,11 +109,13 @@ EXPORT_SYMBOL(memchr);
EXPORT_SYMBOL(__memzero);

/* user mem (segment) */
EXPORT_SYMBOL(__strnlen_user);
EXPORT_SYMBOL(__strncpy_from_user);

#ifdef CONFIG_MMU
EXPORT_SYMBOL(__copy_from_user);
EXPORT_SYMBOL(__copy_to_user);
EXPORT_SYMBOL(__clear_user);
EXPORT_SYMBOL(__strnlen_user);
EXPORT_SYMBOL(__strncpy_from_user);

EXPORT_SYMBOL(__get_user_1);
EXPORT_SYMBOL(__get_user_2);
Expand All @@ -123,6 +125,7 @@ EXPORT_SYMBOL(__put_user_1);
EXPORT_SYMBOL(__put_user_2);
EXPORT_SYMBOL(__put_user_4);
EXPORT_SYMBOL(__put_user_8);
#endif

/* crypto hash */
EXPORT_SYMBOL(sha_transform);
Expand Down
8 changes: 8 additions & 0 deletions arch/arm/kernel/vmlinux.lds.S
Original file line number Diff line number Diff line change
Expand Up @@ -80,14 +80,20 @@ SECTIONS
*(.exit.text)
*(.exit.data)
*(.exitcall.exit)
#ifndef CONFIG_MMU
*(.fixup)
*(__ex_table)
#endif
}

.text : { /* Real text segment */
_text = .; /* Text and read-only data */
*(.text)
SCHED_TEXT
LOCK_TEXT
#ifdef CONFIG_MMU
*(.fixup)
#endif
*(.gnu.warning)
*(.rodata)
*(.rodata.*)
Expand Down Expand Up @@ -142,7 +148,9 @@ SECTIONS
*/
. = ALIGN(32);
__start___ex_table = .;
#ifdef CONFIG_MMU
*(__ex_table)
#endif
__stop___ex_table = .;

/*
Expand Down
13 changes: 8 additions & 5 deletions arch/arm/lib/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -6,28 +6,31 @@

lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
copy_page.o delay.o findbit.o memchr.o memcpy.o \
delay.o findbit.o memchr.o memcpy.o \
memmove.o memset.o memzero.o setbit.o \
strncpy_from_user.o strnlen_user.o \
strchr.o strrchr.o \
testchangebit.o testclearbit.o testsetbit.o \
getuser.o putuser.o clear_user.o \
ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
ucmpdi2.o lib1funcs.o div64.o sha1.o \
io-readsb.o io-writesb.o io-readsl.o io-writesl.o

mmu-y := clear_user.o copy_page.o getuser.o putuser.o

# the code in uaccess.S is not preemption safe and
# probably faster on ARMv3 only
ifeq ($(CONFIG_PREEMPT),y)
lib-y += copy_from_user.o copy_to_user.o
mmu-y += copy_from_user.o copy_to_user.o
else
ifneq ($(CONFIG_CPU_32v3),y)
lib-y += copy_from_user.o copy_to_user.o
mmu-y += copy_from_user.o copy_to_user.o
else
lib-y += uaccess.o
mmu-y += uaccess.o
endif
endif

lib-$(CONFIG_MMU) += $(mmu-y)

ifeq ($(CONFIG_CPU_32v3),y)
lib-y += io-readsw-armv3.o io-writesw-armv3.o
else
Expand Down
5 changes: 1 addition & 4 deletions arch/arm/lib/backtrace.S
Original file line number Diff line number Diff line change
Expand Up @@ -97,16 +97,13 @@ ENTRY(c_backtrace)
b 1007f

/*
* Fixup for LDMDB
* Fixup for LDMDB. Note that this must not be in the fixup section.
*/
.section .fixup,"ax"
.align 0
1007: ldr r0, =.Lbad
mov r1, frame
bl printk
ldmfd sp!, {r4 - r8, pc}
.ltorg
.previous

.section __ex_table,"a"
.align 3
Expand Down
67 changes: 35 additions & 32 deletions arch/arm/mm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@ config CPU_ARM610
select CPU_32v3
select CPU_CACHE_V3
select CPU_CACHE_VIVT
select CPU_COPY_V3
select CPU_TLB_V3
select CPU_COPY_V3 if MMU
select CPU_TLB_V3 if MMU
help
The ARM610 is the successor to the ARM3 processor
and was produced by VLSI Technology Inc.
Expand All @@ -31,8 +31,8 @@ config CPU_ARM710
select CPU_32v3
select CPU_CACHE_V3
select CPU_CACHE_VIVT
select CPU_COPY_V3
select CPU_TLB_V3
select CPU_COPY_V3 if MMU
select CPU_TLB_V3 if MMU
help
A 32-bit RISC microprocessor based on the ARM7 processor core
designed by Advanced RISC Machines Ltd. The ARM710 is the
Expand All @@ -50,8 +50,8 @@ config CPU_ARM720T
select CPU_ABRT_LV4T
select CPU_CACHE_V4
select CPU_CACHE_VIVT
select CPU_COPY_V4WT
select CPU_TLB_V4WT
select CPU_COPY_V4WT if MMU
select CPU_TLB_V4WT if MMU
help
A 32-bit RISC processor with 8kByte Cache, Write Buffer and
MMU built around an ARM7TDMI core.
Expand All @@ -68,8 +68,8 @@ config CPU_ARM920T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_COPY_V4WB
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
help
The ARM920T is licensed to be produced by numerous vendors,
and is used in the Maverick EP9312 and the Samsung S3C2410.
Expand All @@ -89,8 +89,8 @@ config CPU_ARM922T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_COPY_V4WB
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
help
The ARM922T is a version of the ARM920T, but with smaller
instruction and data caches. It is used in Altera's
Expand All @@ -108,8 +108,8 @@ config CPU_ARM925T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_COPY_V4WB
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
help
The ARM925T is a mix between the ARM920T and ARM926T, but with
different instruction and data caches. It is used in TI's OMAP
Expand All @@ -126,8 +126,8 @@ config CPU_ARM926T
select CPU_32v5
select CPU_ABRT_EV5TJ
select CPU_CACHE_VIVT
select CPU_COPY_V4WB
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
help
This is a variant of the ARM920. It has slightly different
instruction sequences for cache and TLB operations. Curiously,
Expand All @@ -144,8 +144,8 @@ config CPU_ARM1020
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_COPY_V4WB
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
help
The ARM1020 is the 32K cached version of the ARM10 processor,
with an addition of a floating-point unit.
Expand All @@ -161,8 +161,8 @@ config CPU_ARM1020E
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_COPY_V4WB
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
depends on n

# ARM1022E
Expand All @@ -172,8 +172,8 @@ config CPU_ARM1022
select CPU_32v5
select CPU_ABRT_EV4T
select CPU_CACHE_VIVT
select CPU_COPY_V4WB # can probably do better
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU # can probably do better
select CPU_TLB_V4WBI if MMU
help
The ARM1022E is an implementation of the ARMv5TE architecture
based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
Expand All @@ -189,8 +189,8 @@ config CPU_ARM1026
select CPU_32v5
select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
select CPU_CACHE_VIVT
select CPU_COPY_V4WB # can probably do better
select CPU_TLB_V4WBI
select CPU_COPY_V4WB if MMU # can probably do better
select CPU_TLB_V4WBI if MMU
help
The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
based upon the ARM10 integer core.
Expand All @@ -207,8 +207,8 @@ config CPU_SA110
select CPU_ABRT_EV4
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
select CPU_COPY_V4WB
select CPU_TLB_V4WB
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WB if MMU
help
The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
is available at five speeds ranging from 100 MHz to 233 MHz.
Expand All @@ -227,7 +227,7 @@ config CPU_SA1100
select CPU_ABRT_EV4
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
select CPU_TLB_V4WB
select CPU_TLB_V4WB if MMU

# XScale
config CPU_XSCALE
Expand All @@ -237,7 +237,7 @@ config CPU_XSCALE
select CPU_32v5
select CPU_ABRT_EV5T
select CPU_CACHE_VIVT
select CPU_TLB_V4WBI
select CPU_TLB_V4WBI if MMU

# XScale Core Version 3
config CPU_XSC3
Expand All @@ -247,7 +247,7 @@ config CPU_XSC3
select CPU_32v5
select CPU_ABRT_EV5T
select CPU_CACHE_VIVT
select CPU_TLB_V4WBI
select CPU_TLB_V4WBI if MMU
select IO_36

# ARMv6
Expand All @@ -258,8 +258,8 @@ config CPU_V6
select CPU_ABRT_EV6
select CPU_CACHE_V6
select CPU_CACHE_VIPT
select CPU_COPY_V6
select CPU_TLB_V6
select CPU_COPY_V6 if MMU
select CPU_TLB_V6 if MMU

# ARMv6k
config CPU_32v6K
Expand All @@ -277,17 +277,17 @@ config CPU_32v6K
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v3
bool
select TLS_REG_EMUL if SMP
select TLS_REG_EMUL if SMP || !MMU
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP

config CPU_32v4
bool
select TLS_REG_EMUL if SMP
select TLS_REG_EMUL if SMP || !MMU
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP

config CPU_32v5
bool
select TLS_REG_EMUL if SMP
select TLS_REG_EMUL if SMP || !MMU
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP

config CPU_32v6
Expand Down Expand Up @@ -334,6 +334,7 @@ config CPU_CACHE_VIVT
config CPU_CACHE_VIPT
bool

if MMU
# The copy-page model
config CPU_COPY_V3
bool
Expand Down Expand Up @@ -372,6 +373,8 @@ config CPU_TLB_V4WBI
config CPU_TLB_V6
bool

endif

#
# CPU supports 36-bit I/O
#
Expand Down
10 changes: 8 additions & 2 deletions arch/arm/mm/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,16 @@
# Makefile for the linux arm-specific parts of the memory manager.
#

obj-y := consistent.o extable.o fault-armv.o \
fault.o flush.o init.o ioremap.o mmap.o \
obj-y := consistent.o extable.o fault.o init.o \
iomap.o

obj-$(CONFIG_MMU) += fault-armv.o flush.o ioremap.o mmap.o \
mm-armv.o

ifneq ($(CONFIG_MMU),y)
obj-y += nommu.o
endif

obj-$(CONFIG_MODULES) += proc-syms.o

obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
Expand Down
2 changes: 0 additions & 2 deletions arch/arm/mm/init.c
Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#define TABLE_SIZE (2 * PTRS_PER_PTE * sizeof(pte_t))

DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);

extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
Expand Down
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