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Merge tag 'pci-v5.4-changes' of git://git.kernel.org/pub/scm/linux/ke…
…rnel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Consolidate _HPP/_HPX stuff in pci-acpi.c and simplify it (Krzysztof Wilczynski) - Fix incorrect PCIe device types and remove dev->has_secondary_link to simplify code that deals with upstream/downstream ports (Mika Westerberg) - After suspend, restore Resizable BAR size bits correctly for 1MB BARs (Sumit Saxena) - Enable PCI_MSI_IRQ_DOMAIN support for RISC-V (Wesley Terpstra) Virtualization: - Add ACS quirks for iProc PAXB (Abhinav Ratna), Amazon Annapurna Labs (Ali Saidi) - Move sysfs SR-IOV functions to iov.c (Kelsey Skunberg) - Remove group write permissions from sysfs sriov_numvfs, sriov_drivers_autoprobe (Kelsey Skunberg) Hotplug: - Simplify pciehp indicator control (Denis Efremov) Peer-to-peer DMA: - Allow P2P DMA between root ports for whitelisted bridges (Logan Gunthorpe) - Whitelist some Intel host bridges for P2P DMA (Logan Gunthorpe) - DMA map P2P DMA requests that traverse host bridge (Logan Gunthorpe) Amazon Annapurna Labs host bridge driver: - Add DT binding and controller driver (Jonathan Chocron) Hyper-V host bridge driver: - Fix hv_pci_dev->pci_slot use-after-free (Dexuan Cui) - Fix PCI domain number collisions (Haiyang Zhang) - Use instance ID bytes 4 & 5 as PCI domain numbers (Haiyang Zhang) - Fix build errors on non-SYSFS config (Randy Dunlap) i.MX6 host bridge driver: - Limit DBI register length (Stefan Agner) Intel VMD host bridge driver: - Fix config addressing issues (Jon Derrick) Layerscape host bridge driver: - Add bar_fixed_64bit property to endpoint driver (Xiaowei Bao) - Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC drivers separately (Xiaowei Bao) Mediatek host bridge driver: - Add MT7629 controller support (Jianjun Wang) Mobiveil host bridge driver: - Fix CPU base address setup (Hou Zhiqiang) - Make "num-lanes" property optional (Hou Zhiqiang) Tegra host bridge driver: - Fix OF node reference leak (Nishka Dasgupta) - Disable MSI for root ports to work around design problem (Vidya Sagar) - Add Tegra194 DT binding and controller support (Vidya Sagar) - Add support for sideband pins and slot regulators (Vidya Sagar) - Add PIPE2UPHY support (Vidya Sagar) Misc: - Remove unused pci_block_cfg_access() et al (Kelsey Skunberg) - Unexport pci_bus_get(), etc (Kelsey Skunberg) - Hide PM, VC, link speed, ATS, ECRC, PTM constants and interfaces in the PCI core (Kelsey Skunberg) - Clean up sysfs DEVICE_ATTR() usage (Kelsey Skunberg) - Mark expected switch fall-through (Gustavo A. R. Silva) - Propagate errors for optional regulators and PHYs (Thierry Reding) - Fix kernel command line resource_alignment parameter issues (Logan Gunthorpe)" * tag 'pci-v5.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (112 commits) PCI: Add pci_irq_vector() and other stubs when !CONFIG_PCI arm64: tegra: Add PCIe slot supply information in p2972-0000 platform arm64: tegra: Add configuration for PCIe C5 sideband signals PCI: tegra: Add support to enable slot regulators PCI: tegra: Add support to configure sideband pins PCI: vmd: Fix shadow offsets to reflect spec changes PCI: vmd: Fix config addressing when using bus offsets PCI: dwc: Add validation that PCIe core is set to correct mode PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root Port PCI: Add ACS quirk for Amazon Annapurna Labs root ports PCI: Add Amazon's Annapurna Labs vendor ID MAINTAINERS: Add PCI native host/endpoint controllers designated reviewer PCI: hv: Use bytes 4 and 5 from instance ID as the PCI domain numbers dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries dt-bindings: PCI: tegra: Add sideband pins configuration entries PCI: tegra: Add Tegra194 PCIe support PCI: Get rid of dev->has_secondary_link flag ...
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Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
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NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) | ||
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This PCIe host controller is based on the Synopsis Designware PCIe IP | ||
and thus inherits all the common properties defined in designware-pcie.txt. | ||
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Required properties: | ||
- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie". | ||
- device_type: Must be "pci" | ||
- power-domains: A phandle to the node that controls power to the respective | ||
PCIe controller and a specifier name for the PCIe controller. Following are | ||
the specifiers for the different PCIe controllers | ||
TEGRA194_POWER_DOMAIN_PCIEX8B: C0 | ||
TEGRA194_POWER_DOMAIN_PCIEX1A: C1 | ||
TEGRA194_POWER_DOMAIN_PCIEX1A: C2 | ||
TEGRA194_POWER_DOMAIN_PCIEX1A: C3 | ||
TEGRA194_POWER_DOMAIN_PCIEX4A: C4 | ||
TEGRA194_POWER_DOMAIN_PCIEX8A: C5 | ||
these specifiers are defined in | ||
"include/dt-bindings/power/tegra194-powergate.h" file. | ||
- reg: A list of physical base address and length pairs for each set of | ||
controller registers. Must contain an entry for each entry in the reg-names | ||
property. | ||
- reg-names: Must include the following entries: | ||
"appl": Controller's application logic registers | ||
"config": As per the definition in designware-pcie.txt | ||
"atu_dma": iATU and DMA registers. This is where the iATU (internal Address | ||
Translation Unit) registers of the PCIe core are made available | ||
for SW access. | ||
"dbi": The aperture where root port's own configuration registers are | ||
available | ||
- interrupts: A list of interrupt outputs of the controller. Must contain an | ||
entry for each entry in the interrupt-names property. | ||
- interrupt-names: Must include the following entries: | ||
"intr": The Tegra interrupt that is asserted for controller interrupts | ||
"msi": The Tegra interrupt that is asserted when an MSI is received | ||
- bus-range: Range of bus numbers associated with this controller | ||
- #address-cells: Address representation for root ports (must be 3) | ||
- cell 0 specifies the bus and device numbers of the root port: | ||
[23:16]: bus number | ||
[15:11]: device number | ||
- cell 1 denotes the upper 32 address bits and should be 0 | ||
- cell 2 contains the lower 32 address bits and is used to translate to the | ||
CPU address space | ||
- #size-cells: Size representation for root ports (must be 2) | ||
- ranges: Describes the translation of addresses for root ports and standard | ||
PCI regions. The entries must be 7 cells each, where the first three cells | ||
correspond to the address as described for the #address-cells property | ||
above, the fourth and fifth cells are for the physical CPU address to | ||
translate to and the sixth and seventh cells are as described for the | ||
#size-cells property above. | ||
- Entries setup the mapping for the standard I/O, memory and | ||
prefetchable PCI regions. The first cell determines the type of region | ||
that is setup: | ||
- 0x81000000: I/O memory region | ||
- 0x82000000: non-prefetchable memory region | ||
- 0xc2000000: prefetchable memory region | ||
Please refer to the standard PCI bus binding document for a more detailed | ||
explanation. | ||
- #interrupt-cells: Size representation for interrupts (must be 1) | ||
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties | ||
Please refer to the standard PCI bus binding document for a more detailed | ||
explanation. | ||
- clocks: Must contain an entry for each entry in clock-names. | ||
See ../clocks/clock-bindings.txt for details. | ||
- clock-names: Must include the following entries: | ||
- core | ||
- resets: Must contain an entry for each entry in reset-names. | ||
See ../reset/reset.txt for details. | ||
- reset-names: Must include the following entries: | ||
- apb | ||
- core | ||
- phys: Must contain a phandle to P2U PHY for each entry in phy-names. | ||
- phy-names: Must include an entry for each active lane. | ||
"p2u-N": where N ranges from 0 to one less than the total number of lanes | ||
- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed | ||
by controller-id. Following are the controller ids for each controller. | ||
0: C0 | ||
1: C1 | ||
2: C2 | ||
3: C3 | ||
4: C4 | ||
5: C5 | ||
- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals | ||
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Optional properties: | ||
- pinctrl-names: A list of pinctrl state names. | ||
It is mandatory for C5 controller and optional for other controllers. | ||
- "default": Configures PCIe I/O for proper operation. | ||
- pinctrl-0: phandle for the 'default' state of pin configuration. | ||
It is mandatory for C5 controller and optional for other controllers. | ||
- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt | ||
- nvidia,update-fc-fixup: This is a boolean property and needs to be present to | ||
improve performance when a platform is designed in such a way that it | ||
satisfies at least one of the following conditions thereby enabling root | ||
port to exchange optimum number of FC (Flow Control) credits with | ||
downstream devices | ||
1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) | ||
2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and | ||
a) speed is Gen-2 and MPS is 256B | ||
b) speed is >= Gen-3 with any MPS | ||
- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM | ||
to be specified in microseconds | ||
- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be | ||
specified in microseconds | ||
- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be | ||
specified in microseconds | ||
- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot | ||
if the platform has one such slot. (Ex:- x16 slot owned by C5 controller | ||
in p2972-0000 platform). | ||
- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot | ||
if the platform has one such slot. (Ex:- x16 slot owned by C5 controller | ||
in p2972-0000 platform). | ||
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Examples: | ||
========= | ||
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Tegra194: | ||
-------- | ||
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pcie@14180000 { | ||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; | ||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; | ||
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ | ||
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ | ||
0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */ | ||
reg-names = "appl", "config", "atu_dma"; | ||
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#address-cells = <3>; | ||
#size-cells = <2>; | ||
device_type = "pci"; | ||
num-lanes = <8>; | ||
linux,pci-domain = <0>; | ||
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pinctrl-names = "default"; | ||
pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; | ||
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clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; | ||
clock-names = "core"; | ||
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resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, | ||
<&bpmp TEGRA194_RESET_PEX0_CORE_0>; | ||
reset-names = "apb", "core"; | ||
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ | ||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | ||
interrupt-names = "intr", "msi"; | ||
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#interrupt-cells = <1>; | ||
interrupt-map-mask = <0 0 0 0>; | ||
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | ||
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nvidia,bpmp = <&bpmp 0>; | ||
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supports-clkreq; | ||
nvidia,aspm-cmrt-us = <60>; | ||
nvidia,aspm-pwr-on-t-us = <20>; | ||
nvidia,aspm-l0s-entrance-latency-us = <3>; | ||
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bus-range = <0x0 0xff>; | ||
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ | ||
0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */ | ||
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ | ||
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vddio-pex-ctl-supply = <&vdd_1v8ao>; | ||
vpcie3v3-supply = <&vdd_3v3_pcie>; | ||
vpcie12v-supply = <&vdd_12v_pcie>; | ||
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phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, | ||
<&p2u_hsio_5>; | ||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; | ||
}; |
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* Amazon Annapurna Labs PCIe host bridge | ||
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Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare | ||
PCI core. It inherits common properties defined in | ||
Documentation/devicetree/bindings/pci/designware-pcie.txt. | ||
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Properties of the host controller node that differ from it are: | ||
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- compatible: | ||
Usage: required | ||
Value type: <stringlist> | ||
Definition: Value should contain | ||
- "amazon,al-alpine-v2-pcie" for alpine_v2 | ||
- "amazon,al-alpine-v3-pcie" for alpine_v3 | ||
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- reg: | ||
Usage: required | ||
Value type: <prop-encoded-array> | ||
Definition: Register ranges as listed in the reg-names property | ||
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- reg-names: | ||
Usage: required | ||
Value type: <stringlist> | ||
Definition: Must include the following entries | ||
- "config" PCIe ECAM space | ||
- "controller" AL proprietary registers | ||
- "dbi" Designware PCIe registers | ||
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Example: | ||
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pcie-external0: pcie@fb600000 { | ||
compatible = "amazon,al-alpine-v3-pcie"; | ||
reg = <0x0 0xfb600000 0x0 0x00100000 | ||
0x0 0xfd800000 0x0 0x00010000 | ||
0x0 0xfd810000 0x0 0x00001000>; | ||
reg-names = "config", "controller", "dbi"; | ||
bus-range = <0 255>; | ||
device_type = "pci"; | ||
#address-cells = <3>; | ||
#size-cells = <2>; | ||
#interrupt-cells = <1>; | ||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | ||
interrupt-map-mask = <0x00 0 0 7>; | ||
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */ | ||
ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>; | ||
}; |
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Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
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NVIDIA Tegra194 P2U binding | ||
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Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High | ||
Speed) each interfacing with 12 and 8 P2U instances respectively. | ||
A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE | ||
interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe | ||
lane. | ||
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Required properties: | ||
- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u". | ||
- reg: Should be the physical address space and length of respective each P2U | ||
instance. | ||
- reg-names: Must include the entry "ctl". | ||
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Required properties for PHY port node: | ||
- #phy-cells: Defined by generic PHY bindings. Must be 0. | ||
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Refer to phy/phy-bindings.txt for the generic PHY binding properties. | ||
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Example: | ||
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p2u_hsio_0: phy@3e10000 { | ||
compatible = "nvidia,tegra194-p2u"; | ||
reg = <0x03e10000 0x10000>; | ||
reg-names = "ctl"; | ||
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#phy-cells = <0>; | ||
}; |
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