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dt-bindings: display/msm: split dpu-sdm845 into DPU and MDSS parts
In order to make the schema more readable, split dpu-sdm845 into the DPU and MDSS parts, each one describing just a single device binding. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/508382/ Link: https://lore.kernel.org/r/20221024164225.3236654-9-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
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Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Qualcomm Display DPU dt properties for SDM845 target | ||
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maintainers: | ||
- Krishna Manikandan <quic_mkrishn@quicinc.com> | ||
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$ref: /schemas/display/msm/dpu-common.yaml# | ||
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properties: | ||
compatible: | ||
items: | ||
- const: qcom,sdm845-dpu | ||
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reg: | ||
items: | ||
- description: Address offset and size for mdp register set | ||
- description: Address offset and size for vbif register set | ||
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reg-names: | ||
items: | ||
- const: mdp | ||
- const: vbif | ||
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clocks: | ||
items: | ||
- description: Display GCC bus clock | ||
- description: Display ahb clock | ||
- description: Display axi clock | ||
- description: Display core clock | ||
- description: Display vsync clock | ||
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clock-names: | ||
items: | ||
- const: gcc-bus | ||
- const: iface | ||
- const: bus | ||
- const: core | ||
- const: vsync | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h> | ||
#include <dt-bindings/clock/qcom,gcc-sdm845.h> | ||
#include <dt-bindings/power/qcom-rpmpd.h> | ||
display-controller@ae01000 { | ||
compatible = "qcom,sdm845-dpu"; | ||
reg = <0x0ae01000 0x8f000>, | ||
<0x0aeb0000 0x2008>; | ||
reg-names = "mdp", "vbif"; | ||
clocks = <&gcc GCC_DISP_AXI_CLK>, | ||
<&dispcc DISP_CC_MDSS_AHB_CLK>, | ||
<&dispcc DISP_CC_MDSS_AXI_CLK>, | ||
<&dispcc DISP_CC_MDSS_MDP_CLK>, | ||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>; | ||
clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; | ||
interrupt-parent = <&mdss>; | ||
interrupts = <0>; | ||
power-domains = <&rpmhpd SDM845_CX>; | ||
operating-points-v2 = <&mdp_opp_table>; | ||
ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
port@0 { | ||
reg = <0>; | ||
endpoint { | ||
remote-endpoint = <&dsi0_in>; | ||
}; | ||
}; | ||
port@1 { | ||
reg = <1>; | ||
endpoint { | ||
remote-endpoint = <&dsi1_in>; | ||
}; | ||
}; | ||
}; | ||
}; | ||
... |
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Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Qualcomm SDM845 Display MDSS | ||
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maintainers: | ||
- Krishna Manikandan <quic_mkrishn@quicinc.com> | ||
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description: | ||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates | ||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree | ||
bindings of MDSS are mentioned for SDM845 target. | ||
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$ref: /schemas/display/msm/mdss-common.yaml# | ||
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properties: | ||
compatible: | ||
items: | ||
- const: qcom,sdm845-mdss | ||
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clocks: | ||
items: | ||
- description: Display AHB clock from gcc | ||
- description: Display core clock | ||
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clock-names: | ||
items: | ||
- const: iface | ||
- const: core | ||
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iommus: | ||
maxItems: 2 | ||
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interconnects: | ||
maxItems: 2 | ||
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interconnect-names: | ||
maxItems: 2 | ||
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patternProperties: | ||
"^display-controller@[0-9a-f]+$": | ||
type: object | ||
properties: | ||
compatible: | ||
const: qcom,sdm845-dpu | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h> | ||
#include <dt-bindings/clock/qcom,gcc-sdm845.h> | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
#include <dt-bindings/power/qcom-rpmpd.h> | ||
display-subsystem@ae00000 { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
compatible = "qcom,sdm845-mdss"; | ||
reg = <0x0ae00000 0x1000>; | ||
reg-names = "mdss"; | ||
power-domains = <&dispcc MDSS_GDSC>; | ||
clocks = <&gcc GCC_DISP_AHB_CLK>, | ||
<&dispcc DISP_CC_MDSS_MDP_CLK>; | ||
clock-names = "iface", "core"; | ||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
iommus = <&apps_smmu 0x880 0x8>, | ||
<&apps_smmu 0xc80 0x8>; | ||
ranges; | ||
display-controller@ae01000 { | ||
compatible = "qcom,sdm845-dpu"; | ||
reg = <0x0ae01000 0x8f000>, | ||
<0x0aeb0000 0x2008>; | ||
reg-names = "mdp", "vbif"; | ||
clocks = <&gcc GCC_DISP_AXI_CLK>, | ||
<&dispcc DISP_CC_MDSS_AHB_CLK>, | ||
<&dispcc DISP_CC_MDSS_AXI_CLK>, | ||
<&dispcc DISP_CC_MDSS_MDP_CLK>, | ||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>; | ||
clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; | ||
interrupt-parent = <&mdss>; | ||
interrupts = <0>; | ||
power-domains = <&rpmhpd SDM845_CX>; | ||
operating-points-v2 = <&mdp_opp_table>; | ||
ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
port@0 { | ||
reg = <0>; | ||
dpu_intf1_out: endpoint { | ||
remote-endpoint = <&dsi0_in>; | ||
}; | ||
}; | ||
port@1 { | ||
reg = <1>; | ||
dpu_intf2_out: endpoint { | ||
remote-endpoint = <&dsi1_in>; | ||
}; | ||
}; | ||
}; | ||
}; | ||
}; | ||
... |