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ARM i.MX: Add common clock support for pllv1
The pllv1 is found on i.MX1, i.M25, i.MX27, i.MX31 and i.MX35. Currently only reading the rate is supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Sascha Hauer
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May 2, 2012
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Original file line number | Diff line number | Diff line change |
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#include <linux/clk.h> | ||
#include <linux/clk-provider.h> | ||
#include <linux/io.h> | ||
#include <linux/slab.h> | ||
#include <linux/kernel.h> | ||
#include <linux/err.h> | ||
#include <mach/common.h> | ||
#include <mach/hardware.h> | ||
#include <mach/clock.h> | ||
#include "clk.h" | ||
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/** | ||
* pll v1 | ||
* | ||
* @clk_hw clock source | ||
* @parent the parent clock name | ||
* @base base address of pll registers | ||
* | ||
* PLL clock version 1, found on i.MX1/21/25/27/31/35 | ||
*/ | ||
struct clk_pllv1 { | ||
struct clk_hw hw; | ||
void __iomem *base; | ||
}; | ||
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#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) | ||
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static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, | ||
unsigned long parent_rate) | ||
{ | ||
struct clk_pllv1 *pll = to_clk_pllv1(hw); | ||
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return mxc_decode_pll(readl(pll->base), parent_rate); | ||
} | ||
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struct clk_ops clk_pllv1_ops = { | ||
.recalc_rate = clk_pllv1_recalc_rate, | ||
}; | ||
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struct clk *imx_clk_pllv1(const char *name, const char *parent, | ||
void __iomem *base) | ||
{ | ||
struct clk_pllv1 *pll; | ||
struct clk *clk; | ||
struct clk_init_data init; | ||
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pll = kmalloc(sizeof(*pll), GFP_KERNEL); | ||
if (!pll) | ||
return ERR_PTR(-ENOMEM); | ||
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pll->base = base; | ||
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init.name = name; | ||
init.ops = &clk_pllv1_ops; | ||
init.flags = 0; | ||
init.parent_names = &parent; | ||
init.num_parents = 1; | ||
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pll->hw.init = &init; | ||
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clk = clk_register(NULL, &pll->hw); | ||
if (IS_ERR(clk)) | ||
kfree(pll); | ||
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return clk; | ||
} |
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