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We'd like to start splitting i915_reg.h into various domain-specific register files and cleaning them up. Let's move the basic macros and type definitions to their own header file that can be including in each of the new split headers. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-7-matthew.d.roper@intel.com
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Matt Roper
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Jan 11, 2022
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,97 @@ | ||
| /* SPDX-License-Identifier: MIT */ | ||
| /* | ||
| * Copyright © 2022 Intel Corporation | ||
| */ | ||
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| #ifndef __I915_REG_DEFS__ | ||
| #define __I915_REG_DEFS__ | ||
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| #include <linux/bitfield.h> | ||
| #include <linux/bits.h> | ||
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| /** | ||
| * REG_BIT() - Prepare a u32 bit value | ||
| * @__n: 0-based bit number | ||
| * | ||
| * Local wrapper for BIT() to force u32, with compile time checks. | ||
| * | ||
| * @return: Value with bit @__n set. | ||
| */ | ||
| #define REG_BIT(__n) \ | ||
| ((u32)(BIT(__n) + \ | ||
| BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ | ||
| ((__n) < 0 || (__n) > 31)))) | ||
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| /** | ||
| * REG_GENMASK() - Prepare a continuous u32 bitmask | ||
| * @__high: 0-based high bit | ||
| * @__low: 0-based low bit | ||
| * | ||
| * Local wrapper for GENMASK() to force u32, with compile time checks. | ||
| * | ||
| * @return: Continuous bitmask from @__high to @__low, inclusive. | ||
| */ | ||
| #define REG_GENMASK(__high, __low) \ | ||
| ((u32)(GENMASK(__high, __low) + \ | ||
| BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ | ||
| __is_constexpr(__low) && \ | ||
| ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) | ||
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| /* | ||
| * Local integer constant expression version of is_power_of_2(). | ||
| */ | ||
| #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) | ||
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| /** | ||
| * REG_FIELD_PREP() - Prepare a u32 bitfield value | ||
| * @__mask: shifted mask defining the field's length and position | ||
| * @__val: value to put in the field | ||
| * | ||
| * Local copy of FIELD_PREP() to generate an integer constant expression, force | ||
| * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). | ||
| * | ||
| * @return: @__val masked and shifted into the field defined by @__mask. | ||
| */ | ||
| #define REG_FIELD_PREP(__mask, __val) \ | ||
| ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ | ||
| BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ | ||
| BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ | ||
| BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ | ||
| BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) | ||
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| /** | ||
| * REG_FIELD_GET() - Extract a u32 bitfield value | ||
| * @__mask: shifted mask defining the field's length and position | ||
| * @__val: value to extract the bitfield value from | ||
| * | ||
| * Local wrapper for FIELD_GET() to force u32 and for consistency with | ||
| * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). | ||
| * | ||
| * @return: Masked and shifted value of the field defined by @__mask in @__val. | ||
| */ | ||
| #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) | ||
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| typedef struct { | ||
| u32 reg; | ||
| } i915_reg_t; | ||
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| #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) | ||
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| #define INVALID_MMIO_REG _MMIO(0) | ||
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| static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg) | ||
| { | ||
| return reg.reg; | ||
| } | ||
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| static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) | ||
| { | ||
| return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); | ||
| } | ||
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| static inline bool i915_mmio_reg_valid(i915_reg_t reg) | ||
| { | ||
| return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); | ||
| } | ||
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| #endif /* __I915_REG_DEFS__ */ |