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Merge tag 'ib-mfd-net-pinctrl-v6.0' of git://git.kernel.org/pub/scm/l…
…inux/kernel/git/lee/mfd Lee Jones says: ==================== Immutable branch between MFD, Net and Pinctrl due for the v6.0 merge window * tag 'ib-mfd-net-pinctrl-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: mfd: ocelot: Add support for the vsc7512 chip via spi dt-bindings: mfd: ocelot: Add bindings for VSC7512 resource: add define macro for register address resources pinctrl: microchip-sgpio: add ability to be used in a non-mmio configuration pinctrl: microchip-sgpio: allow sgpio driver to be used as a module pinctrl: ocelot: add ability to be used in a non-mmio configuration net: mdio: mscc-miim: add ability to be used in a non-mmio configuration mfd: ocelot: Add helper to get regmap from a resource ==================== Link: https://lore.kernel.org/r/YxrjyHcceLOFlT/c@google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Ocelot Externally-Controlled Ethernet Switch | ||
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maintainers: | ||
- Colin Foster <colin.foster@in-advantage.com> | ||
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description: | | ||
The Ocelot ethernet switch family contains chips that have an internal CPU | ||
(VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have | ||
the option to be controlled externally, which is the purpose of this driver. | ||
The switch family is a multi-port networking switch that supports many | ||
interfaces. Additionally, the device can perform pin control, MDIO buses, and | ||
external GPIO expanders. | ||
properties: | ||
compatible: | ||
enum: | ||
- mscc,vsc7512 | ||
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reg: | ||
maxItems: 1 | ||
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"#address-cells": | ||
const: 1 | ||
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"#size-cells": | ||
const: 1 | ||
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spi-max-frequency: | ||
maxItems: 1 | ||
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patternProperties: | ||
"^pinctrl@[0-9a-f]+$": | ||
type: object | ||
$ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml | ||
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"^gpio@[0-9a-f]+$": | ||
type: object | ||
$ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml | ||
properties: | ||
compatible: | ||
enum: | ||
- mscc,ocelot-sgpio | ||
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"^mdio@[0-9a-f]+$": | ||
type: object | ||
$ref: /schemas/net/mscc,miim.yaml | ||
properties: | ||
compatible: | ||
enum: | ||
- mscc,ocelot-miim | ||
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required: | ||
- compatible | ||
- reg | ||
- '#address-cells' | ||
- '#size-cells' | ||
- spi-max-frequency | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
ocelot_clock: ocelot-clock { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <125000000>; | ||
}; | ||
spi { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
soc@0 { | ||
compatible = "mscc,vsc7512"; | ||
spi-max-frequency = <2500000>; | ||
reg = <0>; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
mdio@7107009c { | ||
compatible = "mscc,ocelot-miim"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x7107009c 0x24>; | ||
sw_phy0: ethernet-phy@0 { | ||
reg = <0x0>; | ||
}; | ||
}; | ||
mdio@710700c0 { | ||
compatible = "mscc,ocelot-miim"; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&miim1_pins>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x710700c0 0x24>; | ||
sw_phy4: ethernet-phy@4 { | ||
reg = <0x4>; | ||
}; | ||
}; | ||
gpio: pinctrl@71070034 { | ||
compatible = "mscc,ocelot-pinctrl"; | ||
gpio-controller; | ||
#gpio-cells = <2>; | ||
gpio-ranges = <&gpio 0 0 22>; | ||
reg = <0x71070034 0x6c>; | ||
sgpio_pins: sgpio-pins { | ||
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; | ||
function = "sg0"; | ||
}; | ||
miim1_pins: miim1-pins { | ||
pins = "GPIO_14", "GPIO_15"; | ||
function = "miim"; | ||
}; | ||
}; | ||
gpio@710700f8 { | ||
compatible = "mscc,ocelot-sgpio"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
bus-frequency = <12500000>; | ||
clocks = <&ocelot_clock>; | ||
microchip,sgpio-port-ranges = <0 15>; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&sgpio_pins>; | ||
reg = <0x710700f8 0x100>; | ||
sgpio_in0: gpio@0 { | ||
compatible = "microchip,sparx5-sgpio-bank"; | ||
reg = <0>; | ||
gpio-controller; | ||
#gpio-cells = <3>; | ||
ngpios = <64>; | ||
}; | ||
sgpio_out1: gpio@1 { | ||
compatible = "microchip,sparx5-sgpio-bank"; | ||
reg = <1>; | ||
gpio-controller; | ||
#gpio-cells = <3>; | ||
ngpios = <64>; | ||
}; | ||
}; | ||
}; | ||
}; | ||
... | ||
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// SPDX-License-Identifier: (GPL-2.0 OR MIT) | ||
/* | ||
* Core driver for the Ocelot chip family. | ||
* | ||
* The VSC7511, 7512, 7513, and 7514 can be controlled internally via an | ||
* on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is | ||
* intended to be the bus-agnostic glue between, for example, the SPI bus and | ||
* the child devices. | ||
* | ||
* Copyright 2021-2022 Innovative Advantage Inc. | ||
* | ||
* Author: Colin Foster <colin.foster@in-advantage.com> | ||
*/ | ||
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#include <linux/bits.h> | ||
#include <linux/device.h> | ||
#include <linux/export.h> | ||
#include <linux/iopoll.h> | ||
#include <linux/ioport.h> | ||
#include <linux/kernel.h> | ||
#include <linux/mfd/core.h> | ||
#include <linux/mfd/ocelot.h> | ||
#include <linux/module.h> | ||
#include <linux/regmap.h> | ||
#include <linux/types.h> | ||
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#include <soc/mscc/ocelot.h> | ||
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#include "ocelot.h" | ||
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#define REG_GCB_SOFT_RST 0x0008 | ||
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#define BIT_SOFT_CHIP_RST BIT(0) | ||
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#define VSC7512_MIIM0_RES_START 0x7107009c | ||
#define VSC7512_MIIM1_RES_START 0x710700c0 | ||
#define VSC7512_MIIM_RES_SIZE 0x024 | ||
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#define VSC7512_PHY_RES_START 0x710700f0 | ||
#define VSC7512_PHY_RES_SIZE 0x004 | ||
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#define VSC7512_GPIO_RES_START 0x71070034 | ||
#define VSC7512_GPIO_RES_SIZE 0x06c | ||
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#define VSC7512_SIO_CTRL_RES_START 0x710700f8 | ||
#define VSC7512_SIO_CTRL_RES_SIZE 0x100 | ||
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#define VSC7512_GCB_RST_SLEEP_US 100 | ||
#define VSC7512_GCB_RST_TIMEOUT_US 100000 | ||
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static int ocelot_gcb_chip_rst_status(struct ocelot_ddata *ddata) | ||
{ | ||
int val, err; | ||
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err = regmap_read(ddata->gcb_regmap, REG_GCB_SOFT_RST, &val); | ||
if (err) | ||
return err; | ||
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return val; | ||
} | ||
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int ocelot_chip_reset(struct device *dev) | ||
{ | ||
struct ocelot_ddata *ddata = dev_get_drvdata(dev); | ||
int ret, val; | ||
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/* | ||
* Reset the entire chip here to put it into a completely known state. | ||
* Other drivers may want to reset their own subsystems. The register | ||
* self-clears, so one write is all that is needed and wait for it to | ||
* clear. | ||
*/ | ||
ret = regmap_write(ddata->gcb_regmap, REG_GCB_SOFT_RST, BIT_SOFT_CHIP_RST); | ||
if (ret) | ||
return ret; | ||
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return readx_poll_timeout(ocelot_gcb_chip_rst_status, ddata, val, !val, | ||
VSC7512_GCB_RST_SLEEP_US, VSC7512_GCB_RST_TIMEOUT_US); | ||
} | ||
EXPORT_SYMBOL_NS(ocelot_chip_reset, MFD_OCELOT); | ||
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static const struct resource vsc7512_miim0_resources[] = { | ||
DEFINE_RES_REG_NAMED(VSC7512_MIIM0_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim0"), | ||
DEFINE_RES_REG_NAMED(VSC7512_PHY_RES_START, VSC7512_PHY_RES_SIZE, "gcb_phy"), | ||
}; | ||
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static const struct resource vsc7512_miim1_resources[] = { | ||
DEFINE_RES_REG_NAMED(VSC7512_MIIM1_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim1"), | ||
}; | ||
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static const struct resource vsc7512_pinctrl_resources[] = { | ||
DEFINE_RES_REG_NAMED(VSC7512_GPIO_RES_START, VSC7512_GPIO_RES_SIZE, "gcb_gpio"), | ||
}; | ||
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static const struct resource vsc7512_sgpio_resources[] = { | ||
DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"), | ||
}; | ||
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static const struct mfd_cell vsc7512_devs[] = { | ||
{ | ||
.name = "ocelot-pinctrl", | ||
.of_compatible = "mscc,ocelot-pinctrl", | ||
.num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources), | ||
.resources = vsc7512_pinctrl_resources, | ||
}, { | ||
.name = "ocelot-sgpio", | ||
.of_compatible = "mscc,ocelot-sgpio", | ||
.num_resources = ARRAY_SIZE(vsc7512_sgpio_resources), | ||
.resources = vsc7512_sgpio_resources, | ||
}, { | ||
.name = "ocelot-miim0", | ||
.of_compatible = "mscc,ocelot-miim", | ||
.of_reg = VSC7512_MIIM0_RES_START, | ||
.use_of_reg = true, | ||
.num_resources = ARRAY_SIZE(vsc7512_miim0_resources), | ||
.resources = vsc7512_miim0_resources, | ||
}, { | ||
.name = "ocelot-miim1", | ||
.of_compatible = "mscc,ocelot-miim", | ||
.of_reg = VSC7512_MIIM1_RES_START, | ||
.use_of_reg = true, | ||
.num_resources = ARRAY_SIZE(vsc7512_miim1_resources), | ||
.resources = vsc7512_miim1_resources, | ||
}, | ||
}; | ||
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static void ocelot_core_try_add_regmap(struct device *dev, | ||
const struct resource *res) | ||
{ | ||
if (dev_get_regmap(dev, res->name)) | ||
return; | ||
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ocelot_spi_init_regmap(dev, res); | ||
} | ||
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static void ocelot_core_try_add_regmaps(struct device *dev, | ||
const struct mfd_cell *cell) | ||
{ | ||
int i; | ||
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for (i = 0; i < cell->num_resources; i++) | ||
ocelot_core_try_add_regmap(dev, &cell->resources[i]); | ||
} | ||
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int ocelot_core_init(struct device *dev) | ||
{ | ||
int i, ndevs; | ||
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ndevs = ARRAY_SIZE(vsc7512_devs); | ||
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for (i = 0; i < ndevs; i++) | ||
ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]); | ||
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL); | ||
} | ||
EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT); | ||
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MODULE_DESCRIPTION("Externally Controlled Ocelot Chip Driver"); | ||
MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>"); | ||
MODULE_LICENSE("GPL"); | ||
MODULE_IMPORT_NS(MFD_OCELOT_SPI); |
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