Merge tag 'mmc-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/gi…

…t/ulfh/mmc

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Share a helper to convert from crypto_profile to mmc_host
   - Respect quirk_max_rate for non-UHS SDIO card too

  MMC host:
   - Add DT bindings for the mmc-slot
   - Clarify DT bindings for the mmc-controller
   - bcm2835: Add support for system-wide suspend/resume PM
   - dw_mmc-exynos: Add support for the exynos8895 variant
   - meson-mx-sdio: Convert DT bindings to dtschema
   - mtk-sd: Fixup use of two register ranges
   - mtk-sd: Add support for ignoring cmd response CRC
   - sdhci-esdhc-imx: enable 'SDHCI_QUIRK_NO_LED' quirk for S32G
   - sdhci-msm: Correctly set the load for the regulator
   - sdhci-msm: Convert to use custom crypto profile
   - sdhci-of-at91: Add support for the microchip sama7d65 variant"

* tag 'mmc-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (25 commits)
  mmc: sdhci-msm: Correctly set the load for the regulator
  mmc: hi3798mv200: Use syscon_regmap_lookup_by_phandle_args
  mmc: Use of_property_present() for non-boolean properties
  dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatible for exynos8895
  mmc: sdhci-msm: convert to use custom crypto profile
  mmc: crypto: add mmc_from_crypto_profile()
  mmc: mtk-sd: Limit getting top_base to SoCs that require it
  dt-bindings: mmc: mtk-sd: Document compatibles that need two register ranges
  mmc: sdhci-acpi: Use devm_platform_ioremap_resource()
  mmc: sdhci-acpi: Remove not so useful error message
  dt-bindings: mmc: convert amlogic,meson-mx-sdio.txt to dtschema
  dt-bindings: mmc: document mmc-slot
  dt-bindings: mmc: controller: remove '|' when not needed
  dt-bindings: mmc: controller: move properties common with slot out to mmc-controller-common
  dt-bindings: mmc: controller: clarify the address-cells description
  mmc: bcm2835: add suspend/resume pm support
  dt-bindings: Drop Bhupesh Sharma from maintainers
  mmc: core: don't include 'pm_wakeup.h' directly
  mmc: mtk-sd: Add support for ignoring cmd response CRC
  mmc: core: Introduce the MMC_RSP_R1B_NO_CRC response
  ...

Documentation/devicetree/bindings/crypto/qcom-qce.yaml

@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm crypto engine driver
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   This document defines the binding for the QCE crypto

Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml

@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
+
+description: |
+  The highspeed MMC host controller on Amlogic SoCs provides an interface
+  for MMC, SD, SDIO and SDHC types of memory cards.
+
+  Supported maximum speeds are the ones of the eMMC standard 4.41 as well
+  as the speed of SD standard 2.0.
+
+  The hardware provides an internal "mux" which allows up to three slots
+  to be controlled. Only one slot can be accessed at a time.
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - amlogic,meson8-sdio
+          - amlogic,meson8b-sdio
+      - const: amlogic,meson-mx-sdio
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: core
+      - const: clkin
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "slot@[0-2]$":
+    $ref: mmc-slot.yaml#
+    description:
+      A node for each slot provided by the MMC controller
+
+    properties:
+      reg:
+        enum: [0, 1, 2]
+
+      bus-width:
+        enum: [1, 4]
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mmc@c1108c20 {
+        compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
+        reg = <0xc1108c20 0x20>;
+        interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
+        clocks = <&clk_core>, <&clk_in>;
+        clock-names = "core", "clkin";
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        slot@1 {
+            compatible = "mmc-slot";
+            reg = <1>;
+            bus-width = <4>;
+        };
+    };

Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml

@@ -22,6 +22,7 @@ properties:
       - items:
           - enum:
               - microchip,sam9x7-sdhci
+              - microchip,sama7d65-sdhci
               - microchip,sama7g5-sdhci
           - const: microchip,sam9x60-sdhci
 

Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml

@@ -38,15 +38,9 @@ properties:
 
   reg:
     minItems: 1
-    maxItems: 2
-    description: |
-      For "marvell,armada-3700-sdhci", two register areas.  The first one
-      for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
-      Voltage Control register.  Please follow the examples with compatible
-      "marvell,armada-3700-sdhci" in below.
-      Please also check property marvell,pad-type in below.
-
-      For other compatible strings, one register area for Xenon IP.
+    items:
+      - description: Xenon IP registers
+      - description: Armada 3700 SoC PHY PAD Voltage Control register
 
   clocks:
     minItems: 1
@@ -61,6 +55,17 @@ properties:
   interrupts:
     maxItems: 1
 
+  marvell,pad-type:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum:
+      - sd
+      - fixed-1-8v
+    description:
+      Type of Armada 3700 SoC PHY PAD Voltage Controller register. If "sd" is
+      selected, SoC PHY PAD is set as 3.3V at the beginning and is switched to
+      1.8V when later in higher speed mode. If "fixed-1-8v" is selected, SoC PHY
+      PAD is fixed 1.8V, such as for eMMC.
+
   marvell,xenon-sdhc-id:
     $ref: /schemas/types.yaml#/definitions/uint32
     minimum: 0
@@ -147,27 +152,18 @@ allOf:
     then:
       properties:
         reg:
-          items:
-            - description: Xenon IP registers
-            - description: Armada 3700 SoC PHY PAD Voltage Control register
-
-        marvell,pad-type:
-          $ref: /schemas/types.yaml#/definitions/string
-          enum:
-            - sd
-            - fixed-1-8v
-          description: |
-            Type of Armada 3700 SoC PHY PAD Voltage Controller register.
-            If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
-            and is switched to 1.8V when later in higher speed mode.
-            If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
-            eMMC.
-            Please follow the examples with compatible
-            "marvell,armada-3700-sdhci" in below.
+          minItems: 2
 
       required:
         - marvell,pad-type
 
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
+        marvell,pad-type: false
+
   - if:
       properties:
         compatible: