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perf vendor events intel: Add uncore event list for Alderlake
Add JSON uncore events for Alderlake to perf. Based on JSON list v1.06: https://download.01.org/perfmon/ADL/ Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lore.kernel.org/lkml/20220224162350.1975130-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
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[ | ||
{ | ||
"BriefDescription": "Number of clocks", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x01", | ||
"EventName": "UNC_M_CLOCKTICKS", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Incoming VC0 read request", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x02", | ||
"EventName": "UNC_M_VC0_REQUESTS_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Incoming VC0 write request", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x03", | ||
"EventName": "UNC_M_VC0_REQUESTS_WR", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Incoming VC1 read request", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x04", | ||
"EventName": "UNC_M_VC1_REQUESTS_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Incoming VC1 write request", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x05", | ||
"EventName": "UNC_M_VC1_REQUESTS_WR", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Incoming read prefetch request from IA", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x0A", | ||
"EventName": "UNC_M_PREFETCH_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Any Rank at Hot state", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x19", | ||
"EventName": "UNC_M_DRAM_THERMAL_HOT", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Any Rank at Warm state", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x1A", | ||
"EventName": "UNC_M_DRAM_THERMAL_WARM", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "incoming read request page status is Page Hit", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x1C", | ||
"EventName": "UNC_M_DRAM_PAGE_HIT_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "incoming read request page status is Page Empty", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x1D", | ||
"EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "incoming read request page status is Page Miss", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x1E", | ||
"EventName": "UNC_M_DRAM_PAGE_MISS_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "incoming write request page status is Page Hit", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x1F", | ||
"EventName": "UNC_M_DRAM_PAGE_HIT_WR", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "incoming write request page status is Page Empty", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x20", | ||
"EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "incoming write request page status is Page Miss", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x21", | ||
"EventName": "UNC_M_DRAM_PAGE_MISS_WR", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Read CAS command sent to DRAM", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x22", | ||
"EventName": "UNC_M_CAS_COUNT_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Write CAS command sent to DRAM", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x23", | ||
"EventName": "UNC_M_CAS_COUNT_WR", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "ACT command for a read request sent to DRAM", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x24", | ||
"EventName": "UNC_M_ACT_COUNT_RD", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "ACT command for a write request sent to DRAM", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x25", | ||
"EventName": "UNC_M_ACT_COUNT_WR", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "ACT command sent to DRAM", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x26", | ||
"EventName": "UNC_M_ACT_COUNT_TOTAL", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "PRE command sent to DRAM for a read/write request", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x27", | ||
"EventName": "UNC_M_PRE_COUNT_PAGE_MISS", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", | ||
"Counter": "0,1,2,3,4", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x28", | ||
"EventName": "UNC_M_PRE_COUNT_IDLE", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)", | ||
"CounterType": "FREERUN", | ||
"EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)", | ||
"Counter": "3", | ||
"CounterType": "FREERUN", | ||
"EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", | ||
"Counter": "1", | ||
"CounterType": "FREERUN", | ||
"EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
}, | ||
{ | ||
"BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", | ||
"Counter": "4", | ||
"CounterType": "FREERUN", | ||
"EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", | ||
"PerPkg": "1", | ||
"Unit": "iMC" | ||
} | ||
] |
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tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
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[ | ||
{ | ||
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", | ||
"Counter": "Fixed", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0xff", | ||
"EventName": "UNC_CLOCK.SOCKET", | ||
"PerPkg": "1", | ||
"Unit": "CLOCK" | ||
}, | ||
{ | ||
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC", | ||
"Counter": "0,1", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x81", | ||
"EventName": "UNC_ARB_TRK_REQUESTS.ALL", | ||
"PerPkg": "1", | ||
"UMask": "0x01", | ||
"Unit": "ARB" | ||
}, | ||
{ | ||
"BriefDescription": "Number of requests allocated in Coherency Tracker", | ||
"Counter": "0,1", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x84", | ||
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", | ||
"PerPkg": "1", | ||
"UMask": "0x01", | ||
"Unit": "ARB" | ||
}, | ||
{ | ||
"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic", | ||
"CounterType": "PGMABLE", | ||
"EventCode": "0x80", | ||
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", | ||
"PerPkg": "1", | ||
"UMask": "0x01", | ||
"Unit": "ARB" | ||
} | ||
] |